Flexible static memory controller (FSMC) RM0090
1343/1422 Doc ID 018909 Rev 4
1. Memory asserts the WAIT signal aligned to NOE/NWE which toggles:
2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 418 and Figure 419 show the number of HCLK clock cycles that are added to the
memory access after WAIT is released by the asynchronous memory (independently of the
above cases).
Figure 418. Asynchronous wait during a read access
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
DATAST 4 HCLK×()max_wait_assertion_time+≥
max_wait_assertion_time address_phase hold_phase+>
DATAST 4 HCLK×()max_wait_assertion_time address_phase– hold_phase–()+≥
A[25:0]
NOE
4HCLK
Memory transaction
NWAIT
D[15:0]
NEx
data driven
by memory
address phase
don’t care
data setup phase
don’t care
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