ST STM32F40 Series User Manual

RM0090 Serial peripheral interface (SPI)
Doc ID 018909 Rev 4 800/1422
Figure 273. Data clock timing diagram
1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.
Data frame format
Data can be shifted out either MSB-first or LSB-first depending on the value of the
LSBFIRST bit in the SPI_CR1 Register.
Each data frame is 8 or 16 bits long depending on the size of the data programmed using
the DFF bit in the SPI_CR1 register. The selected data frame format is applicable for
transmission and/or reception.
27.3.2 Configuring the SPI in slave mode
In the slave configuration, the serial clock is received on the SCK pin from the master
device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data
transfer rate.
Note: It is recommended to enable the SPI slave before the master sends the clock. If not,
undesired data transmission might occur. The data register of the slave needs to be ready
before the first edge of the communication clock or before the end of the ongoing
communication. It is mandatory to have the polarity of the communication clock set to the
steady state value before the slave and the master are enabled.
Follow the procedure below to configure the SPI in slave mode:
CPOL = 1
CPOL = 0
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
NSS
(to slave)
Capture strobe
CPHA =1
CPOL = 1
CPOL = 0
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
NSS
(to slave)
Capture strobe
CPHA =0
8 or 16 bits depending on the Data frame format bit (see DFF in SPI_CR1)
8 or 16 bits depending on the Data frame format bit (see DFF in SPI_CR1)
ai17154b

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English