RM0090 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 018909 Rev 4 912/1422
MII clock sources
To generate both TX_CLK and RX_CLK clock signals, the external PHY must be clocked
with an external 25 MHz as shown in Figure 326. Instead of using an external 25 MHz
quartz to provide this clock, the STM32F4xxmicrocontroller can output this signal on its
MCO pin. In this case, the PLL multiplier has to be configured so as to get the desired
frequency on the MCO pin, from the 25 MHz external quartz.
Figure 326. MII clock sources
29.4.3 Reduced media-independent interface: RMII
The reduced media-independent interface (RMII) specification reduces the pin count
between the microcontroller Ethernet peripheral and the external Ethernet in 10/100 Mbit/s.
According to the IEEE 802.3u standard, an MII contains 16 pins for data and control. The
RMII specification is dedicated to reduce the pin count to 7 pins (a 62.5% decrease in pin
count).
The RMII is instantiated between the MAC and the PHY. This helps translation of the MAC’s
MII into the RMII. The RMII block has the following characteristics:
● It supports 10-Mbit/s and 100-Mbit/s operating rates
● The clock reference must be doubled to 50 MHz
● The same clock reference must be sourced externally to both MAC and external
Ethernet PHY
● It provides independent 2-bit wide (dibit) transmit and receive data paths
STM32
MCO
25 MHz
25 MHz
25 MHz
TX _CLK
For 10/100 Mbit/s
RX _CLK
HSE
802.3 MAC
ai15623
External
PHY
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