RM0090 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 018909 Rev 4 910/1422
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock
whose source is the application clock (AHB clock). The divide factor depends on the clock
range setting in the MII Address register.
Table 162 shows how to set the clock ranges.
29.4.2 Media-independent interface: MII
The media-independent interface (MII) defines the interconnection between the MAC
sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.
Figure 325. Media independent interface signals
● MII_TX_CLK: continuous clock that provides the timing reference for the TX data
transfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s
speed.
● MII_RX_CLK: continuous clock that provides the timing reference for the RX data
transfer. The nominal frequency is: 2.5 MHz at 10 Mbit/s speed; 25 MHz at 100 Mbit/s
speed.
● MII_TX_EN: transmission enable indicates that the MAC is presenting nibbles on the
MII for transmission. It must be asserted synchronously (MII_TX_CLK) with the first
nibble of the preamble and must remain asserted while all nibbles to be transmitted are
presented to the MII.
● MII_TXD[3:0]: transmit data is a bundle of 4 data signals driven synchronously by the
MAC sublayer and qualified (valid data) on the assertion of the MII_TX_EN signal.
Table 162. Clock range
Selection HCLK clock MDC clock
000 60-100 MHz AHB clock / 42
001 100-168 MHz AHB clock / 62
010 20-35 MHz AHB clock / 16
011 35-60 MHz AHB clock / 26
100, 101, 110, 111 Reserved -
STM32
MDC
MDIO
RX_DV
CRS
COL
TX_EN
RX_CLK
RXD[3:0]
RX_ER
TX _CLK
TXD[3:0]
External
PHY
ai15622b
802.3 MAC
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