ST STM32F40 Series User Manual

RM0090 Reset and clock control for (RCC)
Doc ID 018909 Rev 4 148/1422
6.3.14 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
6.3.15 RCC APB1 peripheral clock enable register
for STM32F405xx/07xx and STM32F415xx/17xx(RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
Bit 4 CRYPEN: Cryptographic modules clock enable
Set and cleared by software.
0: cryptographic module clock disabled
1: cryptographic module clock enabled
Bit 3:1 Reserved, must be kept at reset value.
Bit 0 DCMIEN: Camera interface enable
Set and cleared by software.
0: Camera interface clock disabled
1: Camera interface clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109 87654321 0
Reserved
FSMCEN
rw
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 FSMCEN: Flexible static memory controller module clock enable
Set and cleared by software.
0: FSMC module clock disabled
1: FSMC module clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DAC
EN
PWR
EN
Reser-
ved
CAN2
EN
CAN1
EN
Reser-
ved
I2C3
EN
I2C2
EN
I2C1
EN
UART5
EN
UART4
EN
USART3
EN
USART2
EN
Reser-
ved
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Reserved
WWDG
EN
Reserved
TIM14
EN
TIM13
EN
TIM12
EN
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw rw rw rw rw rw rw rw rw rw rw rw

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English