DMA controller (DMA) RM0090
237/1422 Doc ID 018909 Rev 4
9.5.3 DMA low interrupt flag clear register (DMA_LIFCR)
Address offset: 0x08
Reset value: 0x0000 0000
9.5.4 DMA high interrupt flag clear register (DMA_HIFCR)
Address offset: 0x0C
Reset value: 0x0000 0000
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No Direct mode error on stream x
1: A Direct mode error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No FIFO error event on stream x
1: A FIFO error event occurred on stream x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CTCIF3 CHTIF3 CTEIF3 CDMEIF3
Reserved
CFEIF3 CTCIF2 CHTIF2 CTEIF2 CDMEIF2
Reserved
CFEIF2
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CTCIF1 CHTIF1 CTEIF1 CDMEIF1
Reserved
CFEIF1 CTCIF0 CHTIF0 CTEIF0 CDMEIF0
Reserved
CFEIF0
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Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register