Cryptographic processor (CRYP) RM0090
561/1422 Doc ID 018909 Rev 4
Figure 211 and Figure 212 illustrate AES-CTR encryption and decryption, respectively.
Figure 211. AES-CTR mode encryption
1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or
after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when
encoding); P: plain text; IV: Initialization vectors.
IN FIFO
AEA, encrypt
P, 128 b its
OUT FIFO
Cs, 128 bit
plaintext P
ciphertext C
swapping
+
IV0...1(L/R)
O, 128 bits
I, 128 bits
AHB2 data write
(before CRYP
is enabled)
(I + 1) is written
back into IV
at same time
than C is pushed
in OUT FIFO
swapping
C, 128 bits
DATATYPE
DATATYPE
K0...3
128, 192
or 256
Ps, 128 bits
+1
ai16073b
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