ST STM32F40 Series

RM0090 Flexible static memory controller (FSMC)
Doc ID 018909 Rev 4 1324/1422
NOR Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
NOR Flash, multiplexed I/Os
NOR-Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit
(26 address lines).
PSRAM/SRAM, nonmultiplexed I/Os
PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
Table 191. Multiplexed I/O NOR Flash
FSMC signal name I/O Function
CLK O Clock (for synchronous burst)
A[25:16] O Address bus
AD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus
NE[x] O Chip select, x = 1..4
NOE O Output enable
NWE O Write enable
NL(=NADV) O
Latch enable (this signal is called address valid, NADV, by some NOR
Flash devices)
NWAIT I NOR Flash wait input signal to the FSMC
Table 192. Nonmultiplexed I/Os PSRAM/SRAM
FSMC signal name I/O Function
CLK O Clock (only for PSRAM synchronous burst)
A[25:0] O Address bus
D[15:0] I/O Data bidirectional bus
NE[x] O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FSMC
NBL[1] O Upper byte enable (memory signal name: NUB)
NBL[0] O Lowed byte enable (memory signal name: NLB)