General-purpose I/Os (GPIO) RM0090
193/1422 Doc ID 018909 Rev 4
For more details please refer to LCKR register description in Section 7.4.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A..I).
7.3.7 I/O alternate function input/output
Two registers are provided to select one out of the sixteen alternate function inputs/outputs
available for each I/O. With these registers, you can connect an alternate function to some
other pin as required by your application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of one I/O.
To know which functions are multiplexed on each GPIO pin, refer to the datasheets.
Note: The application is allowed to select one of the possible peripheral functions for each I/O at a
time.
7.3.8 External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode, refer to Section 10.2: External interrupt/event controller (EXTI)
and Section 10.2.3: Wakeup event management.
7.3.9 Input configuration
When the I/O port is programmed as Input:
● the output buffer is disabled
● the Schmitt trigger input is activated
● the pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
● The data present on the I/O pin are sampled into the input data register every AHB1
clock cycle
● A read access to the input data register provides the I/O State
Figure 20 shows the input configuration of the I/O port bit.
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