RM0090 Serial peripheral interface (SPI)
Doc ID 018909 Rev 4 796/1422
27.2.2 I
2
S features
● Full duplex communication
● Half-duplex communication (only transmitter or receiver)
● Master or slave operations
● 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
● Data format may be 16-bit, 24-bit or 32-bit
● Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
● Programmable clock polarity (steady state)
● Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave), and Frame Error flag in reception and transmission mode (slave only)
● 16-bit register for transmission and reception with one data register for both channel
sides
● Supported I
2
S protocols:
–I
2
S Phillps standard
– MSB-justified standard (left-justified)
– LSB-justified standard (right-justified)
– PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
● Data direction is always MSB first
● DMA capability for transmission and reception (16-bit wide)
● Master clock may be output to drive an external audio component. Ratio is fixed at
256 × F
S
(where F
S
is the audio sampling frequency)
● Both I
2
S (I2S2 and I2S3) have a dedicated PLL (PLLI2S) to generate an even more
accurate clock.
● I
2
S (I2S2 and I2S3) clock can be derived from an external clock mapped on the
I2S_CKIN pin.
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