RM0090 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 018909 Rev 4 904/1422
29.2.1 MAC core features
● Supports 10/100 Mbit/s data transfer rates with external PHY interfaces
● IEEE 802.3-compliant MII interface to communicate with an external Fast Ethernet
PHY
● Supports both full-duplex and half-duplex operations
– Supports CSMA/CD Protocol for half-duplex operation
– Supports IEEE 802.3x flow control for full-duplex operation
– Optional forwarding of received pause control frames to the user application in full-
duplex operation
– Back-pressure support for half-duplex operation
– Automatic transmission of zero-quanta pause frame on deassertion of flow control
input in full-duplex operation
● Preamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive
paths
● Automatic CRC and pad generation controllable on a per-frame basis
● Options for automatic pad/CRC stripping on receive frames
● Programmable frame length to support Standard frames with sizes up to 16 KB
● Programmable interframe gap (40-96 bit times in steps of 8)
● Supports a variety of flexible address filtering modes:
– Up to four 48-bit perfect (DA) address filters with masks for each byte
– Up to three 48-bit SA address comparison check with masks for each byte
– 64-bit Hash filter (optional) for multicast and unicast (DA) addresses
– Option to pass all multicast addressed frames
– Promiscuous mode support to pass all frames without any filtering for network
monitoring
– Passes all incoming packets (as per filter) with a status report
● Separate 32-bit status returned for transmission and reception packets
● Supports IEEE 802.1Q VLAN tag detection for reception frames
● Separate transmission, reception, and control interfaces to the Application
● Supports mandatory network statistics with RMON/MIB counters (RFC2819/RFC2665)
● MDIO interface for PHY device configuration and management
● Detection of LAN wakeup frames and AMD Magic Packet™ frames
● Receive feature for checksum off-load for received IPv4 and TCP packets
encapsulated by the Ethernet frame
● Enhanced receive feature for checking IPv4 header checksum and TCP, UDP, or ICMP
checksum encapsulated in IPv4 or IPv6 datagrams
● Support Ethernet frame time stamping as described in IEEE 1588-2008. Sixty-four-bit
time stamps are given in each frame’s transmit or receive status
● Two sets of FIFOs: a 2-KB Transmit FIFO with programmable threshold capability, and
a 2-KB Receive FIFO with a configurable threshold (default of 64 bytes)
● Receive Status vectors inserted into the Receive FIFO after the EOF transfer enables
multiple-frame storage in the Receive FIFO without requiring another FIFO to store
those frames’ Receive Status
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