ST STM32F40 Series User Manual

Embedded Flash memory interface RM0090
59/1422 Doc ID 018909 Rev 4
3 Embedded Flash memory interface
3.1 Introduction
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2 Main features
● Flash memory read operations
● Flash memory program/erase operations
● Read / write protections
● Prefetch on I-Code
● 64 cache lines of 128 bits on I-Code
● 8 cache lines of 128 bits on D-Code
Figure 3 shows the Flash memory interface connection inside the system architecture.
Figure 3. Flash memory interface connection inside system architecture
Cortex
core
Ethernet
USB HS
DMA1
DMA2
D-code bus
I-Code bus
Cortex-M4F
I-Code
D-Code
S bus
AHB
periph1
Flash
memory
Flash interface
SRAM and
External
memories
AHB
periph2
FLITF registers
AHB
32-bit
instruction
bus
Access to instruction in Flash memory
Access to data and literal pool in Flash memory
FLITF register access
MS30468V2
CCM data
RAM
AHB
32-bit
data bus
AHB
32-bit
system bus
Flash
memory
bus
128 bits

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English