RM0090 Real-time clock (RTC)
Doc ID 018909 Rev 4 654/1422
23.6.12 RTC shift control register (RTC_SHIFTR)
Address offset: 0x2C
Reset value: 0x0000 0000
Note: This register is write protected. The write access procedure is described in RTC register
write protection on page 630
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S Reserved
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SUBFS[14:0]
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Bit 31 ADD1S: Add one second
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in order to
effectively add a fraction of a second to the clock in an atomic operation.
Bits 31:15 Reserved
Bits 14:0 SUBFS: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler’s counter. Since
this counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / ( PREDIV_S + 1 )
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be
sure that the shadow registers have been updated with the shifted time.
Refer to Section 23.3.8: RTC synchronization.
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