ST STM32F40 Series User Manual

Reset and clock control for (RCC) RM0090
141/1422 Doc ID 018909 Rev 4
6.3.10 RCC APB2 peripheral reset register (RCC_APB2RSTR)
for STM32F405xx/07xx and STM32F415xx/17xx
Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TIM11
RST
TIM10
RST
TIM9
RST
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reser-
ved
SYSCF
G RST
Reser-
ved
SPI1
RST
SDIO
RST
Reserved
ADC
RST
Reserved
USART6
RST
USART1
RST
Reserved
TIM8
RST
TIM1
RST
rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
Set and cleared by software.
0: does not reset TIM11
1: resets TIM14
Bit 17 TIM10RST: TIM10 reset
Set and cleared by software.
0: does not reset TIM10
1: resets TIM10
Bit 16 TIM9RST: TIM9 reset
Set and cleared by software.
0: does not reset TIM9
1: resets TIM9
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGRST: System configuration controller reset
Set and cleared by software.
0: does not reset the System configuration controller
1: resets the System configuration controller
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: does not reset SPI1
1: resets SPI1
Bit 11 SDIORST: SDIO reset
Set and cleared by software.
0: does not reset the SDIO module
1: resets the SDIO module
Bits 10:9 Reserved, must be kept at reset value.

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English