Power controller (PWR) RM0090
99/1422 Doc ID 018909 Rev 4
5.3.4 Stop mode
The Stop mode is based on the Cortex™-M4F deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode. In
Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC
oscillators are disabled. Internal SRAM and register contents are preserved.
By setting the FPDS bit in the PWR_CR register, the Flash memory also enters power-down
mode when the device enters Stop mode. When the Flash memory is in power-down mode,
an additional startup delay is incurred when waking up from Stop mode (see Tabl e 2 1 : S t o p
operating modes).
Entering Stop mode
Refer to Ta bl e 2 2 for details on how to enter the Stop mode.
To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low power mode. This is configured by the LPDS bit of the PWR power control
register (PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx and PWR power
control register (PWR_CR) for STM32F42xxx and STM32F43xxx.
Table 20. Sleep-on-exit entry and exit
Sleep-on-exit Description
Mode entry
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex™-M4F System Control register.
Mode exit
Interrupt: refer to Table 45: Vector table for STM32F405xx/07xx and
STM32F415xx/17xx and Table 46: Vector table for STM32F42xxx and
STM32F43xxx
Wakeup latency None
Table 21. Stop operating modes
Stop mode LPDS bit FPDS bit Wake-up latency
STOP MR
( Main regulator)
0 0 HSI RC startup time
STOP MR-FPD 0 1
HSI RC startup time +
Flash wakeup time from Power Down
mode
STOP LP 1 0
HSI RC startup time +
regulator wakeup time from LP mode
STOP LP-FPD 1 1
HSI RC startup time +
Flash wakeup time from Power Down
mode +
regulator wakeup time from LP mode
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