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RM0090 Ethernet (ETH): media access control (MAC) with DMA controller

Doc ID 018909 Rev 4 924/1422

UDP or ICMP header is not modified. For the second error type, still, the calculated

checksum is inserted into the corresponding header field.

MII/RMII transmit bit order

Each nibble from the MII is transmitted on the RMII a dibit at a time with the order of dibit

transmission shown in Figure 333. Lower order bits (D1 and D0) are transmitted first

followed by higher order bits (D2 and D3).

Figure 333. Transmission bit order

MII/RMII transmit timing diagrams

Figure 334. Transmission with no collision

LSB

MII_TXD[3:0]

MSB

D0 D1

LSB MSB

RMII_TXD[1:0]

Bibit stream

Nibble stream

ai15632

MII_TX_CLK

MII_TX_EN

MII_TXD[3:0]

PR EA MB LE

MII_CS

MII_COL

ai15631

Low

Table 1. Applicable Products1
Table of Contents2
Documentation Conventions47
List of Abbreviations for Registers47
Glossary48
Peripheral Availability48
Memory and Bus Architecture49
System Architecture49
Figure 1. System Architecture for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx Devices50
Figure 2. System Architecture for Stm32F42Xxx and Stm32F43Xxx Devices50
S0: I-Bus51
S1: D-Bus51
S2: S-Bus51
S3, S4: DMA Memory Bus51
S5: DMA Peripheral Bus51
S6: Ethernet DMA Bus51
S7: USB OTG HS DMA Bus51
Busmatrix51
AHB/APB Bridges (APB)52
Memory Organization52
Memory Map52
Table 2. Stm32F4Xx Register Boundary Addresses52
Embedded SRAM55
Flash Memory Overview55
Bit Banding55
Boot Configuration56
Table 3. Boot Modes56
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap57
Embedded Flash Memory Interface59
Introduction59
Main Features59
Figure 3. Flash Memory Interface Connection Inside System Architecture59
Embedded Flash Memory60
Table 5. Flash Module Organization (Stm32F40X and Stm32F41X)60
Read Interface61
Relation between CPU Clock Frequency and Flash Memory Read Time61
Table 6. Flash Memory Organization (Stm32F42X and Stm32F43X)61
Number of Wait States According to CPU Clock (HCLK) Frequency62
Adaptive Real-Time Memory Accelerator (ART Accelerator™)63
Figure 4. Sequential 32-Bit Instruction Execution64
Erase and Program Operations65
Unlocking the Flash Control Register65
Program/Erase Parallelism66
Erase66
Table 8. Program/Erase Parallelism66
Programming67
Interrupts68
Option Bytes68
Description of User Option Bytes68
Table 9. Flash Interrupt Request68
Table 10. Option Byte Organization68
Table 11. Description of the Option Bytes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)69
Table 12. Description of the Option Bytes (Stm32F42Xxx and Stm32F43Xxx)70
Programming User Option Bytes71
Read Protection (RDP)72
Write Protections73
Table 13. Access Versus Read Protection Level73
Figure 5. RDP Levels73
One-Time Programmable Bytes74
Table 14. OTP Area Organization74
Flash Interface Registers75
Flash Access Control Register (FLASH_ACR)75
Flash Key Register (FLASH_KEYR)77
Flash Option Key Register (FLASH_OPTKEYR)77
Flash Status Register (FLASH_SR)78
Flash Control Register (FLASH_CR) for79
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx79
Stm32F42Xxx and Stm32F43Xxx80
Flash Option Control Register (FLASH_OPTCR)82
Flash Option Control Register (FLASH_OPTCR1)83
For Stm32F42Xxx and Stm32F43Xxx83
Flash Interface Register Map84
Table 15. Flash Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)84
Table 16. Flash Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)84
CRC Calculation Unit86
CRC Introduction86
CRC Main Features86
CRC Functional Description86
Figure 6. CRC Calculation Unit Block Diagram86
CRC Registers87
Data Register (CRC_DR)87
Independent Data Register (CRC_IDR)87
Control Register (CRC_CR)88
CRC Register Map88
Table 17. CRC Calculation Unit Register Map and Reset Values88
Power Controller (PWR)89
Power Supplies89
Figure 7. Power Supply Overview89
Independent A/D Converter Supply and Reference Voltage90
Battery Backup Domain90
Voltage Regulator92
Figure 8. Backup Domain92
Power Supply Supervisor94
Power-On Reset (Por)/Power-Down Reset (PDR)94
Brownout Reset (BOR)94
Figure 9. Power-On Reset/Power-Down Reset Waveform94
Programmable Voltage Detector (PVD)95
Figure 10. BOR Thresholds95
Low-Power Modes96
Figure 11. PVD Thresholds96
Slowing down System Clocks97
Peripheral Clock Gating97
Table 18. Low-Power Mode Summary97
Sleep Mode98
Table 19. Sleep-Now Entry and Exit98
Stop Mode99
Table 20. Sleep-On-Exit Entry and Exit99
Table 21. Stop Operating Modes100
Table 22. Stop Mode Entry and Exit100
Standby Mode101
Table 23. Standby Mode Entry and Exit101
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes102
Power Control Registers105
PWR Power Control Register (PWR_CR)105
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx105
PWR Power Control Register (PWR_CR)106
For Stm32F42Xxx and Stm32F43Xxx106
PWR Power Control/Status Register (PWR_CSR)108
PWR Register Map109
Table 24. PWR - Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx109
Table 25. PWR - Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx110
Reset and Clock Control for (RCC)111
Reset111
System Reset111
Power Reset112
Figure 12. Simplified Diagram of the Reset Circuit112
Backup Domain Reset113
Clocks113
Figure 13. Clock Tree114
HSE Clock116
Figure 14. HSE/ LSE Clock Sources116
HSI Clock117
PLL Configuration117
LSE Clock118
LSI Clock118
System Clock (SYSCLK) Selection118
Clock Security System (CSS)118
RTC/AWU Clock119
Watchdog Clock120
Clock-Out Capability120
Internal/External Clock Measurement Using TIM5/TIM11120
Figure 15. Frequency Measurement with TIM5 in Input Capture Mode121
Figure 16. Frequency Measurement with TIM11 in Input Capture Mode122
RCC Registers123
RCC Clock Control Register (RCC_CR)123
RCC PLL Configuration Register (RCC_PLLCFGR)125
RCC Clock Configuration Register (RCC_CFGR)127
RCC Clock Interrupt Register (RCC_CIR)129
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)132
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)134
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)135
RCC APB1 Peripheral Reset Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB1RSTR)135
RCC APB1 Peripheral Reset Register for138
Stm32F42Xxx and Stm32F43Xxx (RCC_APB1RSTR)138
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx141
RCC APB2 Peripheral Reset Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB2RSTR)143
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)145
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)147
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)148
RCC APB1 Peripheral Clock Enable Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB1ENR)148
RCC APB1 Peripheral Clock Enable Register for Stm32F42Xxx and Stm32F43Xxx(RCC_APB1ENR)151
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)154
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx154
RCC APB2 Peripheral Clock Enable Register for Stm32F42Xxx and Stm32F43Xxx(RCC_APB2ENR)156
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx (RCC_AHB1LPENR)158
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_AHB1LPENR)161
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)163
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)164
RCC APB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx (RCC_APB1LPENR)165
RCC APB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB1LPENR)168
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB2LPENR)171
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB2LPENR)173
RCC Backup Domain Control Register (RCC_BDCR)175
RCC Clock Control & Status Register (RCC_CSR)176
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)178
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)179
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)180
RCC Register Map181
Table 26. RCC Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx181
Table 27. RCC Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx183
General-Purpose I/Os (GPIO)185
GPIO Introduction185
GPIO Main Features185
GPIO Functional Description185
Figure 17. Basic Structure of a Five-Volt Tolerant I/O Port Bit186
General-Purpose I/O (GPIO)187
Table 28. Port Bit Configuration Table187
I/O Pin Multiplexer and Mapping188
Table 29. Flexible SWJ-DP Pin Assignment189
Figure 18. Selecting an Alternate Function on Stm32F405Xx/07Xx and Stm32F415Xx/17Xx190
I/O Port Control Registers191
Figure 19. Selecting an Alternate Function on Stm32F42Xxx and Stm32F43Xxx191
I/O Port Data Registers192
I/O Data Bitwise Handling192
GPIO Locking Mechanism192
I/O Alternate Function Input/Output193
External Interrupt/Wakeup Lines193
Input Configuration193
Output Configuration194
Figure 20. Input Floating/Pull Up/Pull down Configurations194
Alternate Function Configuration195
Figure 21. Output Configuration195
Figure 22. Alternate Function Configuration195
Analog Configuration196
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15196
Port Pins196
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins196
Figure 23. High Impedance-Analog Configuration196
Selection of RTC_AF1 and RTC_AF2 Alternate Functions197
Table 30. RTC_AF1 Pin197
GPIO Registers198
GPIO Port Mode Register (Gpiox_Moder) (X = A..I198
Table 31. RTC_AF2 Pin198
GPIO Port Output Type Register (Gpiox_Otyper)199
(X = a199
GPIO Port Output Speed Register (Gpiox_Ospeedr)199
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)199
GPIO Port Input Data Register (Gpiox_Idr) (X = A..I200
GPIO Port Output Data Register (Gpiox_Odr) (X = A..I200
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A..I201
GPIO Port Configuration Lock Register (Gpiox_Lckr)201
(X = a201
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = A..I202
(X = a203
GPIO Register Map203
Table 32. GPIO Register Map and Reset Values203
System Configuration Controller (SYSCFG)206
I/O Compensation Cell206
SYSCFG Registers206
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)206
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx207
For Stm32F42Xxx and Stm32F43Xxx207
SYSCFG External Interrupt Configuration Register 1208
(Syscfg_Exticr1)208
SYSCFG External Interrupt Configuration Register 2209
(Syscfg_Exticr2)209
(Syscfg_Exticr3)209
SYSCFG External Interrupt Configuration Register 4210
(Syscfg_Exticr4)210
Compensation Cell Control Register (SYSCFG_CMPCR)210
SYSCFG Register Maps211
Table 33. SYSCFG Register Map and Reset Values Stm32F405Xx/07Xx and Stm32F415Xx/17Xx211
Table 34. SYSCFG Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)212
DMA Controller (DMA)213
DMA Introduction213
DMA Main Features213
DMA Functional Description215
General Description215
Figure 24. DMA Block Diagram215
Figure 25. System Implementation of the Two DMA Controllers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)216
DMA Transactions217
Figure 26. System Implementation of the Two DMA Controllers (Stm32F42Xxx and Stm32F43Xxx)217
Channel Selection218
Table 35. DMA1 Request Mapping218
Figure 27. Channel Selection218
Arbiter219
Table 36. DMA2 Request Mapping219
DMA Streams220
Source, Destination and Transfer Modes220
Table 37. Source and Destination Address220
Figure 28. Peripheral-To-Memory Mode221
Figure 29. Memory-To-Peripheral Mode222
Pointer Incrementation223
Figure 30. Memory-To-Memory Mode223
Circular Mode224
Double Buffer Mode224
Programmable Data Width, Packing/Unpacking, Endianess225
Table 38. Source and Destination Address Registers in Double Buffer Mode (DBM=1)225
Table 39. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)226
Table 40. Restriction on NDT Versus PSIZE and MSIZE226
Single and Burst Transfers227
Fifo227
Figure 31. FIFO Structure228
Table 41. FIFO Threshold Configurations229
DMA Transfer Completion230
DMA Transfer Suspension231
Flow Controller231
Summary of the Possible DMA Configurations232
Table 42. Possible DMA Configurations232
Stream Configuration Procedure233
Error Management234
DMA Interrupts235
DMA Registers235
DMA Low Interrupt Status Register (DMA_LISR)235
Table 43. DMA Interrupt Requests235
DMA High Interrupt Status Register (DMA_HISR)236
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)237
DMA High Interrupt Flag Clear Register (DMA_HIFCR)237
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0239
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0242
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0242
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar) (X = 0243
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar) (X = 0243
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0244
DMA Register Map245
Table 44. DMA Register Map and Reset Values245
Interrupts and Events249
Nested Vectored Interrupt Controller (NVIC)249
NVIC Features249
Systick Calibration Value Register249
Interrupt and Exception Vectors249
External Interrupt/Event Controller (EXTI)249
Table 45. Vector Table for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx250
Table 46. Vector Table for Stm32F42Xxx and Stm32F43Xxx253
EXTI Main Features257
EXTI Block Diagram257
Wakeup Event Management257
Figure 32. External Interrupt/Event Controller Block Diagram257
Functional Description258
External Interrupt/Event Line Mapping259
Figure 33. External Interrupt/Event GPIO Mapping259
EXTI Registers260
Interrupt Mask Register (EXTI_IMR)260
Event Mask Register (EXTI_EMR)260
Rising Trigger Selection Register (EXTI_RTSR)260
Falling Trigger Selection Register (EXTI_FTSR)261
Software Interrupt Event Register (EXTI_SWIER)261
Pending Register (EXTI_PR)262
EXTI Register Map262
Table 47. External Interrupt/Event Controller Register Map and Reset Values262
Analog-To-Digital Converter (ADC)264
ADC Introduction264
ADC Main Features264
ADC Functional Description264
Figure 34. Single ADC Block Diagram265
ADC On-Off Control266
ADC Clock266
Channel Selection266
Table 48. ADC Pins266
Single Conversion Mode267
Continuous Conversion Mode267
Timing Diagram268
Analog Watchdog268
Figure 35. Timing Diagram268
Scan Mode269
Table 49. Analog Watchdog Channel Selection269
Figure 36. Analog Watchdog's Guarded Area269
Injected Channel Management270
Figure 37. Injected Conversion Latency270
Discontinuous Mode271
Data Alignment272
Channel-Wise Programmable Sampling Time272
Figure 38. Right Alignment of 12-Bit Data272
Figure 39. Left Alignment of 12-Bit Data272
Figure 40. Left Alignment of 6-Bit Data272
Conversion on External Trigger and Trigger Polarity273
Table 50. Configuring the Trigger Polarity273
Table 51. External Trigger for Regular Channels274
Fast Conversion Mode275
Table 52. External Trigger for Injected Channels275
Data Management276
Using the DMA276
Managing a Sequence of Conversions Without Using the DMA276
Conversions Without DMA and Without Overrun Detection277
Multi ADC Mode277
Figure 41. Multi ADC Block Diagram278
Injected Simultaneous Mode280
Regular Simultaneous Mode281
Figure 42. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode281
Figure 43. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode281
Figure 44. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode282
Figure 45. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode282
Interleaved Mode283
Figure 46. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode283
Alternate Trigger Mode284
Figure 47. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode284
Figure 48. Alternate Trigger: Injected Group of each ADC285
Combined Regular/Injected Simultaneous Mode286
Figure 49. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode286
Figure 50. Alternate Trigger: Injected Group of each ADC286
Combined Regular Simultaneous + Alternate Trigger Mode287
Figure 51. Alternate + Regular Simultaneous287
Temperature Sensor288
Figure 52. Case of Trigger Occurring During Injected Conversion288
Figure 53. Temperature Sensor and VREFINT Channel Block Diagram289
Battery Charge Monitoring290
ADC Interrupts290
Table 53. ADC Interrupts290
ADC Registers291
ADC Status Register (ADC_SR)291
ADC Control Register 1 (ADC_CR1)292
ADC Control Register 2 (ADC_CR2)294
ADC Sample Time Register 1 (ADC_SMPR1)297
ADC Sample Time Register 2 (ADC_SMPR2)297
ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1298
ADC Watchdog Higher Threshold Register (ADC_HTR)298
ADC Watchdog Lower Threshold Register (ADC_LTR)298
ADC Regular Sequence Register 1 (ADC_SQR1)299
ADC Regular Sequence Register 2 (ADC_SQR2)299
ADC Regular Sequence Register 3 (ADC_SQR3)300
ADC Injected Sequence Register (ADC_JSQR)300
ADC Injected Data Register X (Adc_Jdrx) (X= 1301
ADC Regular Data Register (ADC_DR)301
ADC Common Status Register (ADC_CSR)303
ADC Common Control Register (ADC_CCR)304
11.13.17 ADC Common Regular Data Register for Dual and Triple Modes307
(Adc_Cdr)307
11.13.18 ADC Register Map307
Table 54. ADC Global Register Map307
Table 55. ADC Register Map and Reset Values for each ADC308
Table 56. ADC Register Map and Reset Values (Common ADC Registers)309
Digital-To-Analog Converter (DAC)310
DAC Introduction310
DAC Main Features310
Table 57. DAC Pins311
Figure 54. DAC Channel Block Diagram311
DAC Functional Description312
DAC Channel Enable312
DAC Output Buffer Enable312
DAC Data Format312
Figure 55. Data Registers in Single DAC Channel Mode312
DAC Conversion313
Figure 56. Data Registers in Dual DAC Channel Mode313
Figure 57. Timing Diagram for Conversion with Trigger Disabled TEN = 0313
DAC Output Voltage314
DAC Trigger Selection314
DMA Request314
Table 58. External Triggers314
Noise Generation315
Figure 58. DAC LFSR Register Calculation Algorithm315
Triangle-Wave Generation316
Figure 59. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation316
Figure 60. DAC Triangle Wave Generation316
Dual DAC Channel Conversion317
Independent Trigger Without Wave Generation317
Figure 61. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation317
Independent Trigger with Single LFSR Generation318
Independent Trigger with Different LFSR Generation318
Independent Trigger with Single Triangle Generation318
Independent Trigger with Different Triangle Generation319
Simultaneous Software Start319
Simultaneous Trigger Without Wave Generation319
Simultaneous Trigger with Single LFSR Generation320
Simultaneous Trigger with Different LFSR Generation320
Simultaneous Trigger with Single Triangle Generation320
Simultaneous Trigger with Different Triangle Generation321
DAC Registers321
DAC Control Register (DAC_CR)321
DAC Software Trigger Register (DAC_SWTRIGR)324
DAC Channel1 12-Bit Right-Aligned Data Holding Register324
(Dac_Dhr12R1)324
DAC Channel1 12-Bit Left Aligned Data Holding Register325
(Dac_Dhr12L1)325
DAC Channel1 8-Bit Right Aligned Data Holding Register325
(Dac_Dhr8R1)325
DAC Channel2 12-Bit Right Aligned Data Holding Register325
(Dac_Dhr12R2)325
DAC Channel2 12-Bit Left Aligned Data Holding Register326
(Dac_Dhr12L2)326
DAC Channel2 8-Bit Right-Aligned Data Holding Register326
(Dac_Dhr8R2)326
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)326
DUAL DAC 12-Bit Left Aligned Data Holding Register327
(Dac_Dhr12Ld)327
DUAL DAC 8-Bit Right Aligned Data Holding Register327
(Dac_Dhr8Rd)327
DAC Channel1 Data Output Register (DAC_DOR1)328
DAC Channel2 Data Output Register (DAC_DOR2)328
DAC Status Register (DAC_SR)328
DAC Register Map329
Table 59. DAC Register Map329
Digital Camera Interface (DCMI)330
DCMI Introduction330
DCMI Main Features330
DCMI Pins330
DCMI Clocks330
Table 60. DCMI Pins330
DCMI Functional Overview331
Figure 62. DCMI Block Diagram331
Figure 63. Top-Level Block Diagram331
DMA Interface332
DCMI Physical Interface332
Table 61. DCMI Signals332
Figure 64. DCMI Signal Waveforms332
Table 62. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)333
Table 63. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)333
Table 64. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)333
Synchronization334
Table 65. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)334
Figure 65. Timing Diagram334
Capture Modes336
Figure 66. Frame Capture Waveforms in Snapshot Mode336
Crop Feature337
Figure 67. Frame Capture Waveforms in Continuous Grab Mode337
Figure 68. Coordinates and Size of the Window after Cropping337
JPEG Format338
Fifo338
Figure 69. Data Capture Waveforms338
Data Format Description339
Data Formats339
Monochrome Format339
RGB Format339
Table 66. Data Storage in Monochrome Progressive Video Format339
Figure 70. Pixel Raster Scan Order339
Ycbcr Format340
DCMI Interrupts340
Table 67. Data Storage in RGB Progressive Video Format340
Table 68. Data Storage in Ycbcr Progressive Video Format340
Table 69. DCMI Interrupts340
DCMI Register Description341
DCMI Control Register 1 (DCMI_CR)341
DCMI Status Register (DCMI_SR)343
DCMI Raw Interrupt Status Register (DCMI_RIS)344
DCMI Interrupt Enable Register (DCMI_IER)345
DCMI Masked Interrupt Status Register (DCMI_MIS)346
DCMI Interrupt Clear Register (DCMI_ICR)347
DCMI Embedded Synchronization Code Register (DCMI_ESCR)347
DCMI Embedded Synchronization Unmask Register (DCMI_ESUR)348
DCMI Crop Window Start (DCMI_CWSTRT)350
DCMI Crop Window Size (DCMI_CWSIZE)350
DCMI Data Register (DCMI_DR)351
DCMI Register Map351
Table 70. DCMI Register Map and Reset Values351
Advanced-Control Timers (TIM1&TIM8)353
TIM1&TIM8 Introduction353
TIM1&TIM8 Main Features353
Figure 71. Advanced-Control Timer Block Diagram355
TIM1&TIM8 Functional Description356
Time-Base Unit356
Counter Modes357
Figure 72. Counter Timing Diagram with Prescaler Division Change from 1 to 2357
Figure 73. Counter Timing Diagram with Prescaler Division Change from 1 to 4357
Figure 74. Counter Timing Diagram, Internal Clock Divided by 1358
Figure 75. Counter Timing Diagram, Internal Clock Divided by 2358
Figure 76. Counter Timing Diagram, Internal Clock Divided by 4359
Figure 77. Counter Timing Diagram, Internal Clock Divided by N359
Figure 78. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)359
Figure 79. Counter Timing Diagram, Update Event When ARPE=1360
Figure 80. Counter Timing Diagram, Internal Clock Divided by 1361
Figure 81. Counter Timing Diagram, Internal Clock Divided by 2361
Figure 82. Counter Timing Diagram, Internal Clock Divided by 4361
Figure 83. Counter Timing Diagram, Internal Clock Divided by N362
Figure 84. Counter Timing Diagram, Update Event When Repetition Counter362
Figure 85. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6363
Figure 86. Counter Timing Diagram, Internal Clock Divided by 2364
Figure 87. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36364
Figure 88. Counter Timing Diagram, Internal Clock Divided by N364
Repetition Counter365
Figure 89. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)365
Figure 90. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)365
Figure 91. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings366
Clock Selection367
Figure 92. Control Circuit in Normal Mode, Internal Clock Divided by 1367
Figure 93. TI2 External Clock Connection Example367
Figure 94. Control Circuit in External Clock Mode 1368
Figure 95. External Trigger Input Block369
Figure 96. Control Circuit in External Clock Mode 2369
Capture/Compare Channels370
Figure 97. Capture/Compare Channel (Example: Channel 1 Input Stage)370
Figure 98. Capture/Compare Channel 1 Main Circuit370
Input Capture Mode371
Figure 99. Output Stage of Capture/Compare Channel (Channel 1 to 3)371
Figure 100. Output Stage of Capture/Compare Channel (Channel 4)371
PWM Input Mode372
Forced Output Mode373
Figure 101. PWM Input Mode Timing373
Output Compare Mode374
PWM Mode375
Figure 102. Output Compare Mode, Toggle on OC1375
Figure 103. Edge-Aligned PWM Waveforms (ARR=8)376
Figure 104. Center-Aligned PWM Waveforms (ARR=8)377
Complementary Outputs and Dead-Time Insertion378
Figure 105. Complementary Output with Dead-Time Insertion378
Figure 106. Dead-Time Waveforms with Delay Greater than the Negative Pulse378
Using the Break Function379
Figure 107. Dead-Time Waveforms with Delay Greater than the Positive Pulse379
Figure 108. Output Behavior in Response to a Break381
Clearing the Ocxref Signal on an External Event382
Figure 109. Clearing Timx Ocxref382
6-Step PWM Generation383
Figure 110. 6-Step Generation, COM Example (OSSR=1)383
One-Pulse Mode384
Figure 111. Example of One Pulse Mode384
Encoder Interface Mode385
Table 71. Counting Direction Versus Encoder Signals386
Figure 112. Example of Counter Operation in Encoder Interface Mode387
Figure 113. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted387
Timer Input XOR Function388
Interfacing with Hall Sensors388
Figure 114. Example of Hall Sensor Interface389
Timx and External Trigger Synchronization390
Figure 115. Control Circuit in Reset Mode390
Figure 116. Control Circuit in Gated Mode391
Figure 117. Control Circuit in Trigger Mode392
Timer Synchronization393
Debug Mode393
Figure 118. Control Circuit in External Clock Mode 2 + Trigger Mode393
TIM1&TIM8 Registers394
TIM1&TIM8 Control Register 1 (Timx_Cr1)394
TIM1&TIM8 Control Register 2 (Timx_Cr2)395
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)398
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)400
Table 72. Timx Internal Trigger Connection400
TIM1&TIM8 Status Register (Timx_Sr)402
TIM1&TIM8 Event Generation Register (Timx_Egr)403
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)405
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)408
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)409
Table 73. Output Control Bits for Complementary Ocx and Ocxn Channels with412
TIM1&TIM8 Counter (Timx_Cnt)413
TIM1&TIM8 Prescaler (Timx_Psc)413
TIM1&TIM8 Auto-Reload Register (Timx_Arr)413
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)414
TIM1&TIM8 Capture/Compare Register 1 (Timx_Ccr1)414
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)415
TIM1&TIM8 Capture/Compare Register 3 (Timx_Ccr3)415
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)416
TIM1&TIM8 Break and Dead-Time Register (Timx_Bdtr)416
TIM1&TIM8 DMA Control Register (Timx_Dcr)418
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)419
TIM1&TIM8 Register Map420
Table 74. TIM1&TIM8 Register Map and Reset Values420
General-Purpose Timers (TIM2 to TIM5)422
TIM2 to TIM5 Introduction422
TIM2 to TIM5 Main Features422
TIM2 to TIM5 Functional Description423
Time-Base Unit423
Figure 119. General-Purpose Timer Block Diagram423
Figure 120. Counter Timing Diagram with Prescaler Division Change from 1 to 2424
Counter Modes425
Figure 121. Counter Timing Diagram with Prescaler Division Change from 1 to 4425
Figure 122. Counter Timing Diagram, Internal Clock Divided by 1426
Figure 123. Counter Timing Diagram, Internal Clock Divided by 2426
Figure 124. Counter Timing Diagram, Internal Clock Divided by 4426
Figure 125. Counter Timing Diagram, Internal Clock Divided by N427
Figure 126. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)427
Figure 127. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)428
Figure 128. Counter Timing Diagram, Internal Clock Divided by 1429
Figure 129. Counter Timing Diagram, Internal Clock Divided by 2429
Figure 130. Counter Timing Diagram, Internal Clock Divided by 4429
Figure 131. Counter Timing Diagram, Internal Clock Divided by N430
Figure 132. Counter Timing Diagram, Update Event430
Figure 133. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6431
Figure 134. Counter Timing Diagram, Internal Clock Divided by 2432
Figure 135. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36432
Figure 136. Counter Timing Diagram, Internal Clock Divided by N432
Figure 137. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)433
Figure 138. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)433
Clock Selection434
Figure 139. Control Circuit in Normal Mode, Internal Clock Divided by 1434
Figure 140. TI2 External Clock Connection Example435
Figure 141. Control Circuit in External Clock Mode 1435
Capture/Compare Channels436
Figure 142. External Trigger Input Block436
Figure 143. Control Circuit in External Clock Mode 2436
Figure 144. Capture/Compare Channel (Example: Channel 1 Input Stage)437
Figure 145. Capture/Compare Channel 1 Main Circuit437
Input Capture Mode438
Figure 146. Output Stage of Capture/Compare Channel (Channel 1)438
PWM Input Mode439
Forced Output Mode440
Figure 147. PWM Input Mode Timing440
Output Compare Mode441
PWM Mode442
Figure 148. Output Compare Mode, Toggle on OC1442
Figure 149. Edge-Aligned PWM Waveforms (ARR=8)443
Figure 150. Center-Aligned PWM Waveforms (ARR=8)444
One-Pulse Mode445
Figure 151. Example of One-Pulse Mode445
Clearing the Ocxref Signal on an External Event446
Figure 152. Clearing Timx Ocxref446
Encoder Interface Mode447
Table 75. Counting Direction Versus Encoder Signals447
Figure 153. Example of Counter Operation in Encoder Interface Mode448
Figure 154. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted448
Timer Input XOR Function449
Timers and External Trigger Synchronization449
Figure 155. Control Circuit in Reset Mode450
Figure 156. Control Circuit in Gated Mode450
Figure 157. Control Circuit in Trigger Mode451
Figure 158. Control Circuit in External Clock Mode 2 + Trigger Mode452
Timer Synchronization453
Figure 159. Master/Slave Timer Example453
Figure 160. Gating Timer 2 with OC1REF of Timer 1454
Figure 161. Gating Timer 2 with Enable of Timer 1455
Figure 162. Triggering Timer 2 with Update of Timer 1456
Figure 163. Triggering Timer 2 with Enable of Timer 1456
Debug Mode458
Figure 164. Triggering Timer 1 and 2 with Timer 1 TI1 Input458
TIM2 to TIM5 Registers459
Timx Control Register 1 (Timx_Cr1)459
Timx Control Register 2 (Timx_Cr2)461
Timx Slave Mode Control Register (Timx_Smcr)462
Timx Dma/Interrupt Enable Register (Timx_Dier)464
Table 76. Timx Internal Trigger Connection464
Timx Status Register (Timx_Sr)465
Timx Event Generation Register (Timx_Egr)467
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)468
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)471
Timx Capture/Compare Enable Register (Timx_Ccer)472
Table 77. Output Control Bit for Standard Ocx Channels473
Timx Counter (Timx_Cnt)474
Timx Prescaler (Timx_Psc)474
Timx Auto-Reload Register (Timx_Arr)474
Timx Capture/Compare Register 1 (Timx_Ccr1)475
Timx Capture/Compare Register 2 (Timx_Ccr2)475
Timx Capture/Compare Register 3 (Timx_Ccr3)476
Timx Capture/Compare Register 4 (Timx_Ccr4)476
Timx DMA Control Register (Timx_Dcr)477
Timx DMA Address for Full Transfer (Timx_Dmar)477
TIM2 Option Register (TIM2_OR)479
TIM5 Option Register (TIM5_OR)480
Timx Register Map480
Table 78. TIM2 to TIM5 Register Map and Reset Values480
General-Purpose Timers (TIM9 to TIM14)482
TIM9 to TIM14 Introduction482
TIM9 to TIM14 Main Features482
TIM9/TIM12 Main Features482
TIM10/TIM11 and TIM13/TIM14 Main Features483
Figure 165. General-Purpose Timer Block Diagram (TIM9 and TIM12)483
Figure 166. General-Purpose Timer Block Diagram (TIM10/11/13/14)484
TIM9 to TIM14 Functional Description485
Time-Base Unit485
Counter Modes486
Figure 167. Counter Timing Diagram with Prescaler Division Change from 1 to 2486
Figure 168. Counter Timing Diagram with Prescaler Division Change from 1 to 4486
Figure 169. Counter Timing Diagram, Internal Clock Divided by 1487
Figure 170. Counter Timing Diagram, Internal Clock Divided by 2487
Figure 171. Counter Timing Diagram, Internal Clock Divided by 4488
Figure 172. Counter Timing Diagram, Internal Clock Divided by N488
Clock Selection489
Figure 175. Control Circuit in Normal Mode, Internal Clock Divided by 1490
Figure 176. TI2 External Clock Connection Example490
Capture/Compare Channels491
Figure 177. Control Circuit in External Clock Mode 1491
Figure 178. Capture/Compare Channel (Example: Channel 1 Input Stage)491
Input Capture Mode492
Figure 179. Capture/Compare Channel 1 Main Circuit492
Figure 180. Output Stage of Capture/Compare Channel (Channel 1)492
PWM Input Mode (Only for TIM9/12)493
Forced Output Mode494
Figure 181. PWM Input Mode Timing494
Output Compare Mode495
PWM Mode496
Figure 182. Output Compare Mode, Toggle on OC1496
One-Pulse Mode497
Figure 183. Edge-Aligned PWM Waveforms (ARR=8)497
Figure 184. Example of One Pulse Mode497
TIM9/12 External Trigger Synchronization498
Figure 185. Control Circuit in Reset Mode499
Figure 186. Control Circuit in Gated Mode500
Figure 187. Control Circuit in Trigger Mode500
Timer Synchronization (TIM9/12)501
Debug Mode501
TIM9 and TIM12 Registers502
TIM9/12 Control Register 1 (Timx_Cr1)502
TIM9/12 Control Register 2 (Timx_Cr2)503
TIM9/12 Slave Mode Control Register (Timx_Smcr)504
Table 79. Timx Internal Trigger Connection505
TIM9/12 Interrupt Enable Register (Timx_Dier)506
TIM9/12 Status Register (Timx_Sr)507
TIM9/12 Event Generation Register (Timx_Egr)508
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)509
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)512
TIM9/12 Counter (Timx_Cnt)513
TIM9/12 Prescaler (Timx_Psc)513
TIM9/12 Auto-Reload Register (Timx_Arr)513
Table 80. Output Control Bit for Standard Ocx Channels513
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)514
TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)514
TIM9/12 Register Map514
Table 81. TIM9/12 Register Map and Reset Values514
TIM10/11/13/14 Registers516
TIM10/11/13/14 Control Register 1 (Timx_Cr1)516
TIM10/11/13/14 Status Register (Timx_Sr)516
TIM10/11/13/14 Event Generation Register (Timx_Egr)517
TIM10/11/13/14 Capture/Compare Mode Register 1519
(Timx_Ccmr1)519
TIM10/11/13/14 Capture/Compare Enable Register521
(Timx_Ccer)521
Table 82. Output Control Bit for Standard Ocx Channels521
TIM10/11/13/14 Counter (Timx_Cnt)522
TIM10/11/13/14 Prescaler (Timx_Psc)522
TIM10/11/13/14 Auto-Reload Register (Timx_Arr)522
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)523
TIM11 Option Register 1 (TIM11_OR)523
TIM10/11/13/14 Register Map524
Table 83. TIM10/11/13/14 Register Map and Reset Values524
Basic Timers (TIM6&TIM7)525
TIM6&TIM7 Introduction525
TIM6&TIM7 Main Features525
Figure 188. Basic Timer Block Diagram525
TIM6&TIM7 Functional Description526
Time-Base Unit526
Counting Mode527
Figure 189. Counter Timing Diagram with Prescaler Division Change from 1 to 2527
Figure 190. Counter Timing Diagram with Prescaler Division Change from 1 to 4527
Figure 191. Counter Timing Diagram, Internal Clock Divided by 1528
Figure 192. Counter Timing Diagram, Internal Clock Divided by 2528
Figure 193. Counter Timing Diagram, Internal Clock Divided by 4529
Figure 194. Counter Timing Diagram, Internal Clock Divided by N529
Clock Source530
Debug Mode530
TIM6&TIM7 Registers531
TIM6&TIM7 Control Register 1 (Timx_Cr1)531
TIM6&TIM7 Control Register 2 (Timx_Cr2)532
TIM6&TIM7 Dma/Interrupt Enable Register (Timx_Dier)532
TIM6&TIM7 Status Register (Timx_Sr)533
TIM6&TIM7 Event Generation Register (Timx_Egr)533
TIM6&TIM7 Counter (Timx_Cnt)533
TIM6&TIM7 Prescaler (Timx_Psc)534
TIM6&TIM7 Auto-Reload Register (Timx_Arr)534
TIM6&TIM7 Register Map535
Table 84. TIM6&TIM7 Register Map and Reset Values535
Independent Watchdog (IWDG)536
IWDG Introduction536
IWDG Main Features536
IWDG Functional Description536
Hardware Watchdog536
Register Access Protection536
Debug Mode537
IWDG Registers537
Table 85. Min/Max IWDG Timeout Period at 32 Khz (LSI)537
Figure 198. Independent Watchdog Block Diagram537
Key Register (IWDG_KR)538
Prescaler Register (IWDG_PR)539
Reload Register (IWDG_RLR)539
Status Register (IWDG_SR)540
IWDG Register Map540
Table 86. IWDG Register Map and Reset Values540
Window Watchdog (WWDG)541
WWDG Introduction541
WWDG Main Features541
WWDG Functional Description541
Figure 199. Watchdog Block Diagram542
How to Program the Watchdog Timeout543
Figure 200. Window Watchdog Timing Diagram543
Debug Mode544
Table 87. Timeout Values at 30 Mhz (F PCLK1 )544
WWDG Registers545
Control Register (WWDG_CR)545
Configuration Register (WWDG_CFR)546
Status Register (WWDG_SR)546
WWDG Register Map547
Table 88. WWDG Register Map and Reset Values547
Cryptographic Processor (CRYP)548
CRYP Introduction548
CRYP Main Features548
Table 89. Number of Cycles Required to Process each 128-Bit Block (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)548
Table 90. Number of Cycles Required to Process each 128-Bit Block (Stm32F42Xxx and Stm32F43Xxx)548
CRYP Functional Description550
Figure 201. Block Diagram (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)550
DES/TDES Cryptographic Core551
Figure 202. Block Diagram (Stm32F42Xxx and Stm32F43Xxx)551
Figure 203. DES/TDES-ECB Mode Encryption553
Figure 204. DES/TDES-ECB Mode Decryption553
Figure 205. DES/TDES-CBC Mode Encryption555
AES Cryptographic Core556
Figure 206. DES/TDES-CBC Mode Decryption556
Figure 207. AES-ECB Mode Encryption557
Figure 208. AES-ECB Mode Decryption558
Figure 209. AES-CBC Mode Encryption559
Figure 210. AES-CBC Mode Decryption560
Figure 211. AES-CTR Mode Encryption561
Figure 212. AES-CTR Mode Decryption562
Figure 213. Initial Counter Block Structure for the Counter Mode562
Data Type567
Table 91. Data Types568
Initialization Vectors - CRYP_IV0569
Figure 214. 64-Bit Block Construction According to DATATYPE569
CRYP Busy State571
Figure 215. Initialization Vectors Use in the TDES-CBC Encryption571
Procedure to Perform an Encryption or a Decryption572
Context Swapping573
CRYP Interrupts575
CRYP DMA Interface575
Figure 216. CRYP Interrupt Mapping Diagram575
CRYP Registers576
CRYP Control Register (CRYP_CR) for576
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx576
CRYP Control Register (CRYP_CR) for579
Stm32F42Xxx and Stm32F43Xxx579
CRYP Status Register (CRYP_SR)581
CRYP Data Input Register (CRYP_DIN)582
CRYP Data Output Register (CRYP_DOUT)583
CRYP DMA Control Register (CRYP_DMACR)584
CRYP Interrupt Mask Set/Clear Register (CRYP_IMSCR)584
CRYP Raw Interrupt Status Register (CRYP_RISR)585
CRYP Masked Interrupt Status Register (CRYP_MISR)585
CRYP Key Registers (CRYP_K0586
CRYP Initialization Vector Registers (CRYP_IV0588
CRYP Context Swap Registers (CRYP_CSGCMCCM0590
CRYP Register Map591
Table 92. CRYP Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx591
Table 93. CRYP Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx592
Random Number Generator (RNG)594
RNG Introduction594
RNG Main Features594
RNG Functional Description594
Figure 217. Block Diagram594
Operation595
Error Management595
RNG Registers595
RNG Control Register (RNG_CR)596
RNG Status Register (RNG_SR)596
RNG Data Register (RNG_DR)597
RNG Register Map598
Table 94. RNG Register Map and Reset Map598
Hash Processor (HASH)599
HASH Introduction599
HASH Main Features599
HASH Functional Description600
Figure 218. Block Diagram for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx600
Figure 219. Block Diagram for Stm32F42Xxx and Stm32F43Xxx601
Duration of the Processing602
Data Type602
Figure 220. Bit, Byte and Half-Word Swapping603
Message Digest Computing604
Message Padding605
Hash Operation606
HMAC Operation606
Context Swapping607
HASH Interrupt609
HASH Registers609
HASH Control Register (HASH_CR) for609
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx609
Figure 221. HASH Interrupt Mapping Diagram609
HASH Control Register (HASH_CR) for612
Stm32F42Xxx and Stm32F43Xxx612
HASH Data Input Register (HASH_DIN)615
HASH Start Register (HASH_STR)616
HASH Digest Registers (HASH_HR0617
HASH Interrupt Enable Register (HASH_IMR)619
HASH Status Register (HASH_SR)620
HASH Context Swap Registers (Hash_Csrx)621
HASH Register Map622
Table 95. HASH Register Map and Reset Values on Stm32F405Xx/07Xx and Stm32F415Xx/17Xx622
Table 96. HASH Register Map and Reset Values on Stm32F42Xxx and Stm32F43Xxx623
Real-Time Clock (RTC)625
Introduction625
RTC Main Features626
RTC Functional Description627
Clock and Prescalers627
Figure 222. RTC Block Diagram627
Real-Time Clock and Calendar628
Programmable Alarms629
Periodic Auto-Wakeup629
RTC Initialization and Configuration630
Reading the Calendar631
Resetting the RTC632
RTC Synchronization633
RTC Reference Clock Detection633
RTC Coarse Digital Calibration634
RTC Smooth Digital Calibration635
Timestamp Function637
Tamper Detection638
Calibration Clock Output639
Alarm Output640
RTC and Low Power Modes640
RTC Interrupts640
Table 97. Effect of Low Power Modes on RTC640
Table 98. Interrupt Control Bits641
RTC Registers642
RTC Time Register (RTC_TR)642
RTC Date Register (RTC_DR)643
RTC Control Register (RTC_CR)644
RTC Initialization and Status Register (RTC_ISR)646
RTC Prescaler Register (RTC_PRER)648
RTC Wakeup Timer Register (RTC_WUTR)649
RTC Calibration Register (RTC_CALIBR)650
RTC Alarm a Register (RTC_ALRMAR)651
RTC Alarm B Register (RTC_ALRMBR)652
RTC Write Protection Register (RTC_WPR)653
RTC Sub Second Register (RTC_SSR)653
RTC Shift Control Register (RTC_SHIFTR)654
RTC Time Stamp Time Register (RTC_TSTR)655
RTC Time Stamp Date Register (RTC_TSDR)656
RTC Timestamp Sub Second Register (RTC_TSSSR)656
RTC Calibration Register (RTC_CALR)657
RTC Tamper and Alternate Function Configuration Register658
(Rtc_Tafcr)658
RTC Alarm a Sub Second Register (RTC_ALRMASSR)660
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)661
RTC Backup Registers (Rtc_Bkpxr)662
RTC Register Map662
Table 99. RTC Register Map and Reset Values662
Controller Area Network (Bxcan)664
Bxcan Introduction664
Bxcan Main Features664
Bxcan General Description665
CAN 2.0B Active Core665
Figure 223. CAN Network Topology665
Control, Status and Configuration Registers666
Tx Mailboxes666
Acceptance Filters666
Bxcan Operating Modes667
Figure 224. Dual CAN Block Diagram667
Initialization Mode668
Normal Mode668
Sleep Mode (Low Power)668
Test Mode669
Silent Mode669
Figure 225. Bxcan Operating Modes669
Loop Back Mode670
Loop Back Combined with Silent Mode670
Figure 226. Bxcan in Silent Mode670
Figure 227. Bxcan in Loop Back Mode670
Debug Mode671
Bxcan Functional Description671
Transmission Handling671
Figure 228. Bxcan in Combined Mode671
Time Triggered Communication Mode673
Reception Handling673
Figure 230. Receive FIFO States673
Identifier Filtering674
Figure 231. Filter Bank Scale Configuration - Register Organization676
Figure 232. Example of Filter Numbering677
Message Storage678
Figure 233. Filtering Mechanism - Example678
Table 100. Transmit Mailbox Mapping679
Table 101. Receive Mailbox Mapping679
Figure 234. CAN Error State Diagram679
Error Management680
Bit Timing680
Figure 235. Bit Timing681
Figure 236. CAN Frames682
Bxcan Interrupts683
Figure 237. Event Flags and Interrupt Generation683
CAN Registers684
Register Access Protection684
CAN Control and Status Registers684
Figure 229. Transmit Mailbox States684
CAN Mailbox Registers694
CAN Filter Registers701
Bxcan Register Map705
Table 102. Bxcan Register Map and Reset Values705
Inter-Integrated Circuit (I 2 C) Interface708
I 2 C Introduction708
I 2 C Main Features708
I 2 C Functional Description709
Mode Selection709
Figure 238. I2C Bus Protocol710
Figure 239. I2C Block Diagram for Stm32F40X/41X710
I2C Slave Mode711
Figure 240. I2C Block Diagram for Stm32F42X/43X711
Figure 241. Transfer Sequence Diagram for Slave Transmitter713
I2C Master Mode714
Figure 242. Transfer Sequence Diagram for Slave Receiver714
Figure 243. Transfer Sequence Diagram for Master Transmitter716
Figure 244. Transfer Sequence Diagram for Master Receiver718
Error Conditions719
Programmable Noise Filter720
Table 103. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)720
SDA/SCL Line Control721
Smbus721
Table 104. Smbus Vs. I2C722
DMA Requests724
Packet Error Checking725
I 2 C Interrupts726
Table 105. I2C Interrupt Requests726
Figure 245. I2C Interrupt Mapping Diagram727
I 2 C Debug Mode728
I 2 C Registers728
I 2 C Control Register 1 (I2C_CR1)728
I 2 C Control Register 2 (I2C_CR2)730
I 2 C Own Address Register 1 (I2C_OAR1)732
I 2 C Own Address Register 2 (I2C_OAR2)732
I 2 C Data Register (I2C_DR)733
I 2 C Status Register 1 (I2C_SR1)733
I 2 C Status Register 2 (I2C_SR2)737
I 2 C Clock Control Register (I2C_CCR)738
I 2 C TRISE Register (I2C_TRISE)739
I 2 C FLTR Register (I2C_FLTR)740
I2C Register Map741
Table 106. I2C Register Map and Reset Values741
Universal Synchronous Asynchronous Receiver Transmitter (USART)742
USART Introduction742
USART Main Features742
USART Functional Description743
Figure 246. USART Block Diagram745
USART Character Description746
Figure 247. Word Length Programming746
Transmitter747
Figure 248. Configurable Stop Bits748
Figure 249. TC/TXE Behavior When Transmitting749
Receiver750
Figure 250. Start Bit Detection When Oversampling by 16 or 8750
Table 107. Noise Detection from Sampled Data753
Figure 251. Data Sampling When Oversampling by 16753
Figure 252. Data Sampling When Oversampling by 8753
Fractional Baud Rate Generation755
Table 108. Error Calculation for Programmed Baud Rates at F756
USART Receiver Tolerance to Clock Deviation764
Multiprocessor Communication765
Table 118. USART Receiver's Tolerance When DIV Fraction Is 0765
Table 119. USART Receiver's Tolerance When Div_Fraction Is Different from 0765
Figure 253. Mute Mode Using Idle Line Detection766
Figure 254. Mute Mode Using Address Mark Detection766
Parity Control767
Table 120. Frame Formats767
LIN (Local Interconnection Network) Mode768
Figure 255. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)769
USART Synchronous Mode770
Figure 256. Break Detection in LIN Mode Vs. Framing Error Detection770
Figure 257. USART Example of Synchronous Transmission771
Figure 258. USART Data Clock Timing Diagram (M=0)771
Single-Wire Half-Duplex Communication772
Figure 259. USART Data Clock Timing Diagram (M=1)772
Figure 260. RX Data Setup/Hold Time772
Smartcard773
Figure 261. ISO 7816-3 Asynchronous Protocol773
Figure 262. Parity Error Detection Using the 1.5 Stop Bits774
Irda SIR ENDEC Block775
Figure 263. Irda SIR ENDEC- Block Diagram776
Figure 264. Irda Data Modulation (3/16) -Normal Mode776
Continuous Communication Using DMA777
Figure 265. Transmission Using DMA778
Hardware Flow Control779
Figure 266. Reception Using DMA779
Figure 267. Hardware Flow Control between 2 Usarts779
Figure 268. RTS Flow Control780
Figure 269. CTS Flow Control780
USART Interrupts781
Table 121. USART Interrupt Requests781
Figure 270. USART Interrupt Mapping Diagram781
USART Mode Configuration782
USART Registers782
Status Register (USART_SR)782
Table 122. USART Mode Configuration782
Data Register (USART_DR)784
Baud Rate Register (USART_BRR)785
Control Register 1 (USART_CR1)785
Control Register 2 (USART_CR2)788
Control Register 3 (USART_CR3)789
Guard Time and Prescaler Register (USART_GTPR)792
USART Register Map793
Table 123. USART Register Map and Reset Values793
Serial Peripheral Interface (SPI)794
SPI Introduction794
SPI and I 2 S Main Features795
SPI Features795
I 2 S Features796
SPI Functional Description797
General Description797
Figure 271. SPI Block Diagram797
Figure 272. Single Master/ Single Slave Application798
Configuring the SPI in Slave Mode800
Figure 273. Data Clock Timing Diagram800
Figure 274. TI Mode - Slave Mode, Single Transfer802
Figure 275. TI Mode - Slave Mode, Continuous Transfer802
Configuring the SPI in Master Mode803
Figure 276. TI Mode - Master Mode, Single Transfer804
Figure 277. TI Mode - Master Mode, Continuous Transfer804
Configuring the SPI for Half-Duplex Communication805
Data Transmission and Reception Procedures805
Figure 278. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0 and RXONLY=0)808
Figure 279. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the808
Figure 280. TXE/BSY Behavior in Master Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the809
Figure 281. TXE/BSY in Slave Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the Case of810
Figure 282. RXNE Behavior in Receive-Only Mode (BIDIRMODE=0 and RXONLY=1) in the Case of811
CRC Calculation812
Figure 283. TXE/BSY Behavior When Transmitting (BIDIRMODE=0 and RXONLY=0) in the Case of812
Status Flags814
Disabling the SPI815
SPI Communication Using DMA (Direct Memory Addressing)816
Figure 284. Transmission Using DMA817
Figure 285. Reception Using DMA817
Error Flags818
SPI Interrupts819
Table 124. SPI Interrupt Requests819
Figure 286. TI Mode Frame Format Error Detection819
S Functional Description820
S General Description820
Figure 287. I 2 S Block Diagram820
I2S Full Duplex821
Figure 288. I2S Full Duplex Block Diagram821
Supported Audio Protocols822
Figure 289. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)823
Figure 290. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)823
Figure 291. Transmitting 0X8Eaa33823
Figure 292. Receiving 0X8Eaa33824
Figure 293. I 2 S Philips Standard (16-Bit Extended to 32-Bit Packet Frame with CPOL = 0)824
Figure 294. Example824
Figure 295. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0825
Figure 296. MSB Justified 24-Bit Frame Length with CPOL = 0825
Figure 297. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0825
Figure 298. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0826
Figure 299. LSB Justified 24-Bit Frame Length with CPOL = 0826
Figure 300. Operations Required to Transmit 0X3478Ae826
Figure 301. Operations Required to Receive 0X3478Ae827
Figure 302. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0827
Figure 303. Example of LSB Justified 16-Bit Extended to 32-Bit Packet Frame827
Clock Generator828
Figure 304. PCM Standard Waveforms (16-Bit)828
Figure 305. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)828
Figure 306. Audio Sampling Frequency Definition829
Figure 307. I S Clock Generator Architecture829
I 2 S Master Mode830
Table 125. Audio Frequency Precision (for PLLM VCO = 1 Mhz or 2 Mhz)830
I 2 S Slave Mode832
Status Flags834
Error Flags835
I 2 S Interrupts836
DMA Features836
Table 126. I836
SPI and I 2 S Registers837
SPI Control Register 1 (SPI_CR1) (Not Used in I 2 S Mode)837
SPI Control Register 2 (SPI_CR2)839
SPI Status Register (SPI_SR)840
SPI Data Register (SPI_DR)841
SPI CRC Polynomial Register (SPI_CRCPR)841
Mode)841
SPI RX CRC Register (SPI_RXCRCR)842
Mode)842
SPI TX CRC Register (SPI_TXCRCR)842
SPI_I 2 S Configuration Register (SPI_I2SCFGR)843
SPI_I 2 S Prescaler Register (SPI_I2SPR)844
SPI Register Map845
Table 127. SPI Register Map and Reset Values845
Secure Digital Input/Output Interface (SDIO)846
SDIO Main Features846
SDIO Bus Topology846
Figure 308. SDIO "No Response" and "No Data" Operations847
Figure 309. SDIO (Multiple) Block Read Operation847
Figure 310. SDIO (Multiple) Block Write Operation848
Figure 311. SDIO Sequential Read Operation848
Figure 312. SDIO Sequential Write Operation848
SDIO Functional Description849
Figure 313. SDIO Block Diagram849
SDIO Adapter850
Table 128. SDIO I/O Definitions850
Figure 314. SDIO Adapter850
Figure 315. Control Unit851
Figure 316. SDIO Adapter Command Path852
Figure 317. Command Path State Machine (CPSM)853
Table 129. Command Format854
Figure 318. SDIO Command Transfer854
Table 130. Short Response Format855
Table 131. Long Response Format855
Table 132. Command Path Status Flags855
Figure 319. Data Path856
Figure 320. Data Path State Machine (DPSM)857
Table 133. Data Token Format858
Table 134. Transmit FIFO Status Flags859
SDIO APB2 Interface860
Table 135. Receive FIFO Status Flags860
Card Functional Description861
Card Identification Mode861
Card Reset861
Operating Voltage Range Validation861
Card Identification Process862
Block Write863
Block Read863
Stream Access, Stream Write and Stream Read (Multimediacard Only)864
Erase: Group Erase and Sector Erase865
Wide Bus Selection or Deselection866
Protection Management866
Card Status Register869
Table 136. Card Status870
SD Status Register872
Table 137. SD Status872
Table 138. Speed Class Code Field874
Table 139. Performance Move Field874
Table 140. AU_SIZE Field875
Table 141. Maximum au Size875
Table 142. Erase Size Field875
Table 143. Erase Timeout Field875
SD I/O Mode876
Table 144. Erase Offset Field876
Commands and Responses877
Table 145. Block-Oriented Write Commands878
Table 146. Block-Oriented Write Protection Commands879
Table 147. Erase Commands879
Table 148. I/O Mode Commands879
Response Formats880
Table 149. Lock Card880
Table 150. Application-Specific Commands880
R1 (Normal Response Command)881
R1B881
R2 (CID, CSD Register)881
Table 151. R1 Response881
Table 152. R2 Response881
R3 (OCR Register)882
R4 (Fast I/O)882
R4B882
Table 153. R3 Response882
Table 154. R4 Response882
Table 155. R4B Response882
R5 (Interrupt Request)883
Table 156. R5 Response883
SDIO I/O Card-Specific Operations884
SDIO I/O Read Wait Operation by SDIO_D2 Signalling884
Table 157. R6 Response884
SDIO Read Wait Operation by Stopping SDIO_CK885
SDIO Suspend/Resume Operation885
SDIO Interrupts885
CE-ATA Specific Operations885
Command Completion Signal Disable885
Command Completion Signal Enable886
CE-ATA Interrupt886
Aborting CMD61886
HW Flow Control886
SDIO Registers887
SDIO Power Control Register (SDIO_POWER)887
SDI Clock Control Register (SDIO_CLKCR)887
SDIO Argument Register (SDIO_ARG)889
SDIO Command Register (SDIO_CMD)890
SDIO Command Response Register (SDIO_RESPCMD)891
SDIO Response 1891
Table 158. Response Type and Sdio_Respx Registers891
SDIO Data Timer Register (SDIO_DTIMER)892
SDIO Data Length Register (SDIO_DLEN)892
SDIO Data Control Register (SDIO_DCTRL)893
SDIO Data Counter Register (SDIO_DCOUNT)894
SDIO Status Register (SDIO_STA)895
SDIO Interrupt Clear Register (SDIO_ICR)896
SDIO Mask Register (SDIO_MASK)898
SDIO FIFO Counter Register (SDIO_FIFOCNT)900
SDIO Data FIFO Register (SDIO_FIFO)901
SDIO Register Map901
Table 159. SDIO Register Map901
Ethernet (ETH): Media Access Control (MAC) with DMA Controller903
Ethernet Introduction903
Ethernet Main Features903
MAC Core Features904
DMA Features905
PTP Features905
Ethernet Pins906
Table 160. Alternate Function Mapping906
Ethernet Functional Description: SMI, MII and RMII907
Station Management Interface: SMI907
Figure 321. ETH Block Diagram907
Table 161. Management Frame Format908
Figure 322. SMI Interface Signals908
Figure 323. MDIO Timing and Frame Structure - Write Cycle909
Figure 324. MDIO Timing and Frame Structure - Read Cycle909
Media-Independent Interface: MII910
Table 162. Clock Range910
Figure 325. Media Independent Interface Signals910
Table 163. TX Interface Signal Encoding911
Table 164. RX Interface Signal Encoding911
Reduced Media-Independent Interface: RMII912
Figure 326. MII Clock Sources912
MII/RMII Selection913
Figure 327. Reduced Media-Independent Interface Signals913
Figure 328. RMII Clock Sources913
Ethernet Functional Description: MAC 802.3914
Figure 329. Clock Scheme914
MAC 802.3 Frame Format915
Figure 330. Address Field Format916
Figure 331. MAC Frame Format917
MAC Frame Transmission918
Figure 332. Tagged MAC Frame Format918
Figure 333. Transmission Bit Order924
Figure 334. Transmission with no Collision924
MAC Frame Reception925
Figure 335. Transmission with Collision925
Figure 336. Frame Transmission in MMI and RMII Modes925
Table 165. Frame Statuses927
Figure 337. Receive Bit Order929
MAC Interrupts930
Figure 338. Reception with no Error930
Figure 339. Reception with Errors930
Figure 340. Reception with False Carrier Indication930
MAC Filtering931
Figure 341. MAC Core Interrupt Masking Scheme931
Table 166. Destination Address Filtering933
MAC Loopback Mode934
MAC Management Counters: MMC934
Table 167. Source Address Filtering934
Power Management: PMT935
Figure 342. Wakeup Frame Filter Register936
Precision Time Protocol (IEEE1588 PTP)938
Figure 343. Networked Time Synchronization939
Figure 344. System Time Update Using the Fine Correction Method941
Figure 345. PTP Trigger Output to TIM2 ITR1 Connection943
Ethernet Functional Description: DMA Controller Operation944
Figure 346. PPS Output944
Initialization of a Transfer Using DMA945
Host Bus Burst Access945
Figure 347. Descriptor Ring and Chain Structure945
Host Data Buffer Alignment946
Buffer Size Calculations946
DMA Arbiter947
Error Response to DMA947
Tx DMA Configuration947
Figure 348. Txdma Operation in Default Mode949
Figure 349. Txdma Operation in OSF Mode951
Figure 350. Normal Transmit Descriptor952
Figure 351. Enhanced Transmit Descriptor957
Rx DMA Configuration958
Figure 352. Receive DMA Operation959
Figure 353. Normal Rx DMA Descriptor Structure961
Table 168. Receive Descriptor 0 - Encoding for Bits 7, 5 and963
Figure 354. Enhanced Receive Descriptor Field Format with IEEE1588 Time Stamp Enabled968
DMA Interrupts970
Ethernet Interrupts971
Figure 355. Interrupt Scheme971
Ethernet Register Descriptions972
MAC Register Description972
Figure 356. Ethernet MAC Remote Wakeup Frame Filter Register (ETH_MACRWUFFR)981
MMC Register Description991
IEEE 1588 Time Stamp Registers996
DMA Register Description1003
Ethernet Register Maps1017
Table 170. Ethernet Register Map and Reset Values1017
USB On-The-Go Full-Speed (OTG_FS)1021
OTG_FS Introduction1021
OTG_FS Main Features1022
General Features1022
Host-Mode Features1023
Peripheral-Mode Features1023
OTG_FS Functional Description1024
OTG Full-Speed Core1024
Figure 357. Block Diagram1024
Full-Speed OTG PHY1025
OTG Dual Role Device (DRD)1026
ID Line Detection1026
HNP Dual Role Device1026
Figure 358. OTG A-B Device Connection1026
SRP Dual Role Device1027
USB Peripheral1027
SRP-Capable Peripheral1028
Peripheral States1028
Figure 359. USB Peripheral-Only Connection1028
Peripheral Endpoints1029
USB Host1031
SRP-Capable Host1032
USB Host States1032
Figure 360. USB Host-Only Connection1032
Host Channels1034
Host Scheduler1035
SOF Trigger1036
Host Sofs1036
Figure 361. SOF Connectivity1036
Peripheral Sofs1037
Power Options1037
Dynamic Update of the OTG_FS_HFIR Register1038
Figure 362. Updating OTG_FS_HFIR Dynamically1038
USB Data Fifos1039
Peripheral FIFO Architecture1039
Peripheral Rx FIFO1039
Figure 363. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping1039
Peripheral Tx Fifos1040
Host FIFO Architecture1040
Host Rx FIFO1040
Figure 364. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping1040
Host Tx Fifos1041
FIFO RAM Allocation1041
Device Mode1041
Host Mode1042
USB System Performance1042
OTG_FS Interrupts1043
OTG_FS Control and Status Registers1044
Figure 365. Interrupt Hierarchy1044
CSR Memory Map1045
Table 171. Core Global Control and Status Registers (Csrs)1046
Figure 366. CSR Memory Map1046
Table 172. Host-Mode Control and Status Registers (Csrs)1047
Table 173. Device-Mode Control and Status Registers1048
OTG_FS Global Registers1050
Table 174. Data FIFO (DFIFO) Access Register Map1050
Table 175. Power and Clock Gating Control and Status Registers1050
Host-Mode Registers1072
Device-Mode Registers1083
Table 176. Minimum Duration for Soft Disconnect1085
OTG_FS Power and Clock Gating Control Register1105
(Otg_Fs_Pcgcctl)1105
OTG_FS Register Map1106
Table 177. OTG_FS Register Map and Reset Values1106
OTG_FS Programming Model1113
Core Initialization1113
Host Initialization1114
Device Initialization1114
Host Programming Model1115
Figure 367. Transmit FIFO Write Task1116
Figure 368. Receive FIFO Read Task1117
Figure 369. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions1119
Figure 370. Bulk/Control in Transactions1122
Figure 371. Normal Interrupt OUT/IN Transactions1124
Figure 372. Normal Isochronous OUT/IN Transactions1129
Device Programming Model1132
Operational Model1134
Figure 373. Receive FIFO Packet Read1135
Figure 374. Processing a SETUP Packet1137
Figure 375. Bulk out Transaction1143
Worst Case Response Time1151
OTG Programming Model1152
Figure 376. TRDT Max Timing Case1152
Figure 377. A-Device SRP1153
Figure 378. B-Device SRP1154
Figure 379. A-Device HNP1155
Figure 380. B-Device HNP1157
USB On-The-Go High-Speed (OTG_HS)1159
OTG_HS Introduction1159
OTG_HS Main Features1160
General Features1160
Host-Mode Features1161
Peripheral-Mode Features1161
OTG_HS Functional Description1162
High-Speed OTG PHY1162
External Full-Speed OTG PHY Using the I2C Interface1162
Embedded Full-Speed OTG PHY1162
Figure 381. USB OTG Interface Block Diagram1162
OTG Dual-Role Device1163
ID Line Detection1163
HNP Dual Role Device1163
SRP Dual-Role Device1163
USB Functional Description in Peripheral Mode1164
SRP-Capable Peripheral1164
Peripheral States1164
Peripheral Endpoints1165
USB Functional Description on Host Mode1168
SRP-Capable Host1168
USB Host States1168
Host Channels1170
Host Scheduler1171
SOF Trigger1172
Host Sofs1172
Peripheral Sofs1173
USB_HS Power Modes1174
Dynamic Update of the OTG_HS_HFIR Register1174
FIFO RAM Allocation1175
Peripheral Mode1175
Host Mode1175
Figure 382. Updating OTG_HS_HFIR Dynamically1175
OTG_HS Interrupts1176
OTG_HS Control and Status Registers1177
Figure 383. Interrupt Hierarchy1177
CSR Memory Map1179
Table 178. Core Global Control and Status Registers (Csrs)1179
Figure 384. CSR Memory Map1179
Table 179. Host-Mode Control and Status Registers (Csrs)1180
Table 180. Device-Mode Control and Status Registers1181
Table 181. Data FIFO (DFIFO) Access Register Map1183
Table 182. Power and Clock Gating Control and Status Registers1183
OTG_HS Global Registers1184
Host-Mode Registers1208
Device-Mode Registers1220
Table 183. Minimum Duration for Soft Disconnect1223
OTG_HS Power and Clock Gating Control Register1247
(Otg_Hs_Pcgcctl)1247
OTG_HS Register Map1248
Table 184. OTG_HS Register Map and Reset Values1248
OTG_HS Programming Model1260
Core Initialization1260
Host Initialization1261
Device Initialization1262
DMA Mode1262
Host Programming Model1262
Figure 385. Transmit FIFO Write Task1265
Figure 386. Receive FIFO Read Task1266
Figure 387. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - DMA1268
Mode1268
Figure 388. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - Slave1269
Figure 389. Bulk/Control in Transactions - DMA Mode1272
Figure 390. Bulk/Control in Transactions - Slave Mode1273
Figure 391. Normal Interrupt OUT/IN Transactions - DMA Mode1275
Figure 392. Normal Interrupt OUT/IN Transactions - Slave Mode1276
Figure 393. Normal Isochronous OUT/IN Transactions - DMA Mode1281
Figure 394. Normal Isochronous OUT/IN Transactions - Slave Mode1282
Device Programming Model1290
Operational Model1292
Figure 395. Receive FIFO Packet Read in Slave Mode1293
Figure 396. Processing a SETUP Packet1295
Figure 397. Slave Mode Bulk out Transaction1301
Worst Case Response Time1309
OTG Programming Model1310
Figure 398. TRDT Max Timing Case1310
Figure 399. A-Device SRP1311
Figure 400. B-Device SRP1312
Figure 401. A-Device HNP1313
Figure 402. B-Device HNP1315
Flexible Static Memory Controller (FSMC)1317
FSMC Main Features1317
Block Diagram1318
Figure 403. FSMC Block Diagram1318
AHB Interface1319
Supported Memories and Transactions1319
External Device Address Mapping1320
NOR/PSRAM Address Mapping1320
Figure 404. FSMC Memory Banks1320
NAND/PC Card Address Mapping1321
Table 185. NOR/PSRAM Bank Selection1321
Table 186. External Memory Address1321
Table 187. Memory Mapping and Timing Registers1321
NOR Flash/Psram Controller1322
Table 188. NAND Bank Selections1322
External Memory Interface Signals1323
Table 189. Programmable NOR/PSRAM Access Parameters1323
Table 190. Nonmultipled I/O nor Flash1323
Table 191. Multiplexed I/O nor Flash1324
Table 192. Nonmultiplexed I/Os PSRAM/SRAM1324
Supported Memories and Transactions1325
Table 193. Multiplexed I/O PSRAM1325
Table 194. nor Flash/Psram Controller: Example of Supported Memories1325
General Timing Rules1326
NOR Flash/Psram Controller Asynchronous Transactions1327
Figure 405. Mode1 Read Accesses1327
Table 195. Fsmc_Bcrx Bit Fields1328
Figure 406. Mode1 Write Accesses1328
Table 196. Fsmc_Btrx Bit Fields1329
Figure 407. Modea Read Accesses1330
Figure 408. Modea Write Accesses1330
Table 197. Fsmc_Bcrx Bit Fields1331
Table 198. Fsmc_Btrx Bit Fields1331
Table 199. Fsmc_Bwtrx Bit Fields1332
Figure 409. Mode2 and Mode B Read Accesses1332
Figure 410. Mode2 Write Accesses1333
Figure 411. Modeb Write Accesses1333
Table 200. Fsmc_Bcrx Bit Fields1334
Table 201. Fsmc_Btrx Bit Fields1334
Table 202. Fsmc_Bwtrx Bit Fields1335
Figure 412. Mode C Read Accesses1335
Table 203. Fsmc_Bcrx Bit Fields1336
Figure 413. Mode C Write Accesses1336
Table 204. Fsmc_Btrx Bit Fields1337
Table 205. Fsmc_Bwtrx Bit Fields1337
Figure 414. Mode D Read Accesses1338
Figure 415. Mode D Write Accesses1338
Table 206. Fsmc_Bcrx Bit Fields1339
Table 207. Fsmc_Btrx Bit Fields1339
Table 208. Fsmc_Bwtrx Bit Fields1340
Figure 416. Multiplexed Read Accesses1340
Table 209. Fsmc_Bcrx Bit Fields1341
Figure 417. Multiplexed Write Accesses1341
Table 210. Fsmc_Btrx Bit Fields1342
Figure 418. Asynchronous Wait During a Read Access1343
Synchronous Burst Transactions1345
Table 211. Fsmc_Bcrx Bit Fields1347
Figure 421. Synchronous Multiplexed Read Mode - NOR, PSRAM (CRAM)1347
Table 212. Fsmc_Btrx Bit Fields1348
Table 213. Fsmc_Bcrx Bit Fields1349
Figure 422. Synchronous Multiplexed Write Mode - PSRAM (CRAM)1349
Table 214. Fsmc_Btrx Bit Fields1350
NOR/PSRAM Control Registers1351
NAND Flash/Pc Card Controller1357
External Memory Interface Signals1358
Table 215. Programmable NAND/PC Card Access Parameters1358
Table 216. 8-Bit NAND Flash1358
Table 217. 16-Bit NAND Flash1359
Table 218. 16-Bit PC Card1359
NAND Flash / PC Card Supported Memories and Transactions1360
Timing Diagrams for NAND and PC Card1360
Table 219. Supported Memories and Transactions1360
NAND Flash Operations1361
Figure 423. NAND/PC Card Controller Timing for Common Memory Access1361
NAND Flash Pre-Wait Functionality1362
Figure 424. Access to Non 'CE Don't Care' NAND-Flash1362
Error Correction Code Computation ECC (NAND Flash)1363
PC Card/Compactflash Operations1363
Table 220. 16-Bit PC-Card Signals and Access Type1364
NAND Flash/Pc Card Control Registers1366
Table 221. ECC Result Relevant Bits1372
FSMC Register Map1373
Table 222. FSMC Register Map1373
Debug Support (DBG)1375
Overview1375
Figure 425. Block Diagram of STM32 MCU and Cortex™-M4F-Level Debug Support1375
Reference ARM Documentation1376
SWJ Debug Port (Serial Wire and JTAG)1376
Mechanism to Select the JTAG-DP or the SW-DP1377
Pinout and Debug Port Pins1377
Figure 426. SWJ Debug Port1377
SWJ Debug Port Pins1378
Flexible SWJ-DP Pin Assignment1378
Table 223. SWJ Debug Port Pins1378
Table 224. Flexible SWJ-DP Pin Assignment1378
Internal Pull-Up and Pull-Down on JTAG Pins1379
Using Serial Wire and Releasing the Unused Debug Pins as Gpios1380
Stm32F4Xx JTAG TAP Connection1380
Figure 427. JTAG TAP Connections1381
ID Codes and Locking Mechanism1382
MCU Device ID Code1382
Boundary Scan TAP1382
Cortex™-M4F TAP1382
Cortex™-M4F JEDEC-106 ID Code1383
JTAG Debug Port1383
Table 225. JTAG Debug Port Data Registers1383
SW Debug Port1385
SW Protocol Introduction1385
SW Protocol Sequence1385
Table 226. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]1385
SW-DP State Machine (Reset, Idle States, ID Code)1386
Table 227. Packet Request (8-Bits)1386
Table 228. ACK Response (3 Bits)1386
Table 229. DATA Transfer (33 Bits)1386
DP and AP Read/Write Accesses1387
SW-DP Registers1387
Table 230. SW-DP Registers1387
SW-AP Registers1388
AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP1389
Table 231. Cortex™-M4F AHB-AP Registers1389
Core Debug1390
Table 232. Core Debug Registers1390
Capability of the Debugger Host to Connect under System Reset1391
FPB (Flash Patch Breakpoint)1391
DWT (Data Watchpoint Trigger)1392
ITM (Instrumentation Trace Macrocell)1392
General Description1392
Time Stamp Packets, Synchronization and Overflow Packets1392
Table 233. Main ITM Registers1393
ETM (Embedded Trace Macrocell)1394
General Description1394
Signal Protocol, Packet Types1394
Main ETM Registers1395
Configuration Example1395
MCU Debug Component (DBGMCU)1395
Debug Support for Low-Power Modes1395
Table 234. Main ETM Registers1395
Debug Support for Timers, Watchdog, Bxcan and I1396
13961396
Debug MCU Configuration Register1396
Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)1398
Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)1399
TPIU (Trace Port Interface Unit)1400
Introduction1400
Figure 428. TPIU Block Diagram1400
TRACE Pin Assignment1401
Table 235. Asynchronous TRACE Pin Assignment1401
Table 236. Synchronous TRACE Pin Assignment1401
TPUI Formatter1402
Table 237. Flexible TRACE Pin Assignment1402
TPUI Frame Synchronization Packets1403
Transmission of the Synchronization Frame Packet1403
Synchronous Mode1403
Asynchronous Mode1404
TRACECLKIN Connection Inside the Stm32F4Xx1404
TPIU Registers1405
Table 238. Important TPIU Registers1405
33.17.10 Example of Configuration1406
DBG Register Map1406
Table 239. DBG Register Map and Reset Values1406
Device Electronic Signature1407
Unique Device ID Register (96 Bits)1407
Flash Size1408
Revision History1413
Table 240. Document Revision History1413
Figure 419. Asynchronous Wait During a Write Access1421
Figure 420. Wait Configurations1421

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English

ST STM32F40 Series User Manual

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ST STM32F40 Series Specifications

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