ST STM32F40 Series User Manual

Memory and bus architecture RM0090
49/1422 Doc ID 018909 Rev 4
2 Memory and bus architecture
2.1 System architecture
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
● Eight masters:
– Cortex™-M4F core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
– Ethernet DMA bus
– USB OTG HS DMA bus
● Seven slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM1 (112 KB)
– Auxiliary internal SRAM2 (16 KB)
– Auxiliary internal SRAM3 (64 KB) available only on STM32F42xxx and
STM32F43xxx devices
– AHB1 peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
–FSMC
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1 and Figure 2.
Note: The 64-Kbyte CCM (core coupled memory) data RAM is not part of the bus matrix (see
Figure 1: System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices and
Figure 2: System architecture for STM32F42xxx and STM32F43xxx devices). It can be
accessed only through the CPU.

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English