ST STM32F40 Series

RM0090 General-purpose timers (TIM2 to TIM5)
Doc ID 018909 Rev 4 432/1422
Figure 134. Counter timing diagram, internal clock divided by 2
Figure 135. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 136. Counter timing diagram, internal clock divided by N
0002 0000 0001 0002 0003
CNT_EN
TImer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0003
0001
Counter underflow
Update event (UEV)
CK_INT
CK_INT
0036 0035
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0034
0035
Counter overflow (cnt_ovf)
Update event (UEV)
Timer clock = CK_CNT
Counter register
00
20
1F
Update interrupt flag (UIF)
Counter underflow
Update event (UEV)
CK_INT
01