ST STM32F40 Series User Manual

System configuration controller (SYSCFG) RM0090
207/1422 Doc ID 018909 Rev 4
8.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)
for STM32F405xx/07xx and STM32F415xx/17xx
Address offset: 0x04
Reset value: 0x0000 0000
8.2.3 SYSCFG peripheral mode configuration register (SYSCFG_PMC)
for STM32F42xxx and STM32F43xxx
Address offset: 0x04
Reset value: 0x0000 0000
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 MEM_MODE: Memory mapping selection
Set and cleared by software. This bit controls the memory internal mapping at
address 0x0000 0000. After reset these bits take the value selected by the Boot
pins (except for FSMC).
00: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
10: FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000
11: Embedded SRAM (112kB) mapped at 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
MII_RMII
_SEL
Reserved
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 MII_RMII_SEL: Ethernet PHY interface selection
Set and Cleared by software.These bits control the PHY interface for the
Ethernet MAC.
0: MII interface is selected
1: RMII Why interface is selected
Note: This configuration must be done while the MAC is under reset and before
enabling the MAC clocks.
Bits 22:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
MII_RMII
_SEL
Reserved
ADC3D
C2
ADC2D
C2
ADC1D
C2
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English