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RM0090 Secure digital input/output interface (SDIO)

Doc ID 018909 Rev 4 892/1422

28.9.7 SDIO data timer register (SDIO_DTIMER)

Address offset: 0x24

Reset value: 0x0000 0000

The SDIO_DTIMER register contains the data timeout period, in card bus clock periods.

A counter loads the value from the SDIO_DTIMER register, and starts decrementing when

the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0

while the DPSM is in either of these states, the timeout status flag is set.

Note: A data transfer must be written to the data timer register and the data length register before

being written to the data control register.

28.9.8 SDIO data length register (SDIO_DLEN)

Address offset: 0x28

Reset value: 0x0000 0000

The SDIO_DLEN register contains the number of data bytes to be transferred. The value is

loaded into the data counter when data transfer starts.

Note: For a block data transfer, the value in the data length register must be a multiple of the block

size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the

data length register before being written to the data control register.

For an SDIO multibyte transfer the value in the data length register must be between 1 and

512.

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DATATIME

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Bits 31:0 DATATIME: Data timeout period

Data timeout period expressed in card bus clock periods.

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Reserved

DATALENGTH

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Bits 31:25 Reserved, must be kept at reset value

Bits 24:0 DATALENGTH: Data length value

Number of data bytes to be transferred.

ST STM32F40 Series User Manual

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