ST STM32F40 Series User Manual

RM0090 Power controller (PWR)
Doc ID 018909 Rev 4 92/1422
When the backup domain is supplied by V
DD
(analog switch connected to V
DD
), the backup
SRAM is powered from V
DD
which replaces the V
BAT
power supply to save battery life.
When the backup domain is supplied by V
BAT
(analog switch connected to V
BAT
because
V
DD
is not present), the backup SRAM is powered by a dedicated low power regulator. This
regulator can be ON or OFF depending whether the application needs the backup SRAM
function in Standby and V
BAT
modes or not. The power-down of this regulator is controlled
by a dedicated bit, the BRE control bit of the PWR_CSR register (see Section 5.4.3: PWR
power control/status register (PWR_CSR)).
The backup SRAM is not mass erased by an tamper event. It is read protected to prevent
confidential data, such as cryptographic private key, from being accessed. The backup
SRAM can be erased only through the Flash interface when a protection level change from
level 1 to level 0 is requested. Refer to the description of Read protection (RDP) in the Flash
programming manual.
Figure 8. Backup domain
5.1.3 Voltage regulator
An embedded linear voltage regulator supplies all the digital circuitries except for the backup
domain and the Standby circuitry. The regulator output voltage is around 1.2 V.
This voltage regulator requires two external capacitors to be connected to two dedicated
pins, V
CAP_1
and V
CAP_2
available in all packages. Specific pins must be connected either to
V
SS
or V
DD
to activate or deactivate the voltage regulator. These pins depend on the
package.
MS30430V1
Voltage regulator
3.3 -> 1.2 V
1.2 V domain
Backup SRAM
interface
Power switch LP voltage regulator
3.3 -> 1.2 V
Backup SRAM
1.2 V
RTC LSE 32.768 Hz
Backup domain

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English