RM0090 General-purpose timers (TIM2 to TIM5)
Doc ID 018909 Rev 4 436/1422
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 142 gives an overview of the external trigger input block.
Figure 142. External trigger input block
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 143. Control circuit in external clock mode 2
15.3.4 Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
ETR
0
1
TIMx_SMCR
ETP
divider
/1, /2, /4, /8
ETPS[1:0]
ETRP
filter
ETF[3:0]
downcounter
CK_INT
TIMx_SMCR
TIMx_SMCR
ETR pin
CK_INT
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
ETRF
TRGI
TI1F
TI2F
or
or
or
(internal clock)
CK_PSC
ECE
TIMx_SMCR
SMS[2:0]
Counter clock = CK_CNT = CK_PSC
Counter register
35 3634
ETR
CNT_EN
CK_INT
ETRP
ETRF
To Next Page
Loading...
Need help?
General
