Flexible static memory controller (FSMC) RM0090
1347/1422 Doc ID 018909 Rev 4
Figure 421. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held
low.
2. NWAIT polarity is set to 0.
Addr[15:0] data data
addr[25:16]
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
NEx
NOE
NWE
High
NADV
NWAIT
(WAITCFG=1)
A/D[15:0]
1 clock
cycle
1 clock
cycle
(DATALAT + 2)
inserted wait state
Data strobes
ai17723c
CLK cycles
data data
Data strobes
Table 211. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 Reserved 0x000
19 CBURSTRW No effect on synchronous read
18-16 Reserved 0x0
15 ASCYCWAIT 0x0
14 EXTMOD 0x0
13 WAITEN
to be set to 1 if the memory supports this feature, to be kept at 0
otherwise.
12 WREN no effect on synchronous read
11 WAITCFG to be set according to memory
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