ST STM32F40 Series

Revision history RM0090
1421/1422 Doc ID 018909 Rev 4
19-Feb-2013
4
(continued)
FSMC:
Updated write FIFO size in Section 32.1: FSMC main features.
Updated Figure 403: FSMC block diagram.
Updated Section 32.5.4: NOR Flash/PSRAM controller
asynchronous transactions.
Modified differences between Mode B and mode 1 in Section : Mode
2/B - NOR Flash.
Modified differences between Mode C and mode 1 in Section : Mode
C - NOR Flash - OE toggling.
Modified differences between Mode D and mode 1 in Section : Mode
D - asynchronous access with extended address.
Updated NWAIT signal in Figure 418: Asynchronous wait during a
read access, Figure 419: Asynchronous wait during a write access,
Figure 420: Wait configurations, Figure 421: Synchronous
multiplexed read mode - NOR, PSRAM (CRAM), and Figure 422:
Synchronous multiplexed write mode - PSRAM (CRAM).
Updated Table 1 9 5 to Table 214.
Updated Section : SRAM/NOR-Flash chip-select control registers
1..4 (FSMC_BCR1..4).
DEBUG
Updated Figure 425: Block diagram of STM32 MCU and Cortex™-
M4F-level debug support.
Table 240. Document revision history
Date Version Changes