RM0090 Revision history
Doc ID 018909 Rev 4 1420/1422
19-Feb-2013 4
Updated Section 2.3.1: Embedded SRAM.
Updated Figure 1: System architecture for STM32F405xx/07xx and
STM32F415xx/17xx devices, and Figure 2: System architecture for
STM32F42xxx and STM32F43xxx devices. Updated Ta ble 4 :
Memory mapping vs. Boot mode/physical remap. Updated Figure 4:
Sequential 32-bit instruction execution. removed note 1 from Ta bl e 7:
Number of wait states according to CPU clock (HCLK) frequency and
Table 8: Program/erase parallelism.
PWR:
Updated Figure 7: Power supply overview.
Updated Section 5.1.3: Voltage regulator.
Added ADCDC1 bit in Section 5.4.2: PWR power control register
(PWR_CR) for STM32F42xxx and STM32F43xxx.
SYSCFG:
Added ADCxDC2 bit in Section 8.2.3: SYSCFG peripheral mode
configuration register (SYSCFG_PMC) for STM32F42xxx and
STM32F43xxx.
ADC:
Updated Section 11.9.3: Interleaved mode, Section 11.9.4: Alternate
trigger mode, and Section 11.9.6: Combined regular simultaneous +
alternate trigger mode to describe case of interrupted conversion.
Updated Section : Temperature sensor, VREFINT and VBAT internal
channels, Section 11.10: Temperature sensor, and Section 11.11:
Battery charge monitoring.
RTC:
Updated BKP[31:0] bit description in Section 23.6.20: RTC backup
registers (RTC_BKPxR).
I2C:
Updated Section 25.3.5: Programmable noise filter.
Table 240. Document revision history
Date Version Changes
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