RM0090 General-purpose timers (TIM2 to TIM5)
Doc ID 018909 Rev 4 480/1422
15.4.20 TIM5 option register (TIM5_OR)
Address offset: 0x50
Reset value: 0x0000
15.4.21 TIMx register map
TIMx registers are mapped as described in the table below:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TI4_RMP
Reserved
rw rw
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:6 TI4_RMP: Timer Input 4 remap
Set and cleared by software.
00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table
in the datasheets.
01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes
10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes
11: the RTC wakeup interrupt is connected to TIM5_CH4 input for calibration purposes.
Wakeup interrupt should be enabled.
Bits 5:0 Reserved, must be kept at reset value.
Table 78. TIM2 to TIM5 register map and reset values
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
TIMx_CR1
Reserved
CKD
[1:0]
ARPE
CMS
[1:0]
DIR
OPM
URS
UDIS
CEN
Reset value 0000000000
0x04
TIMx_CR2
Reserved
TI1S
MMS[2:0]
CCDS
Reserved
Reset value 00000
0x08
TIMx_SMCR
Reserved
ETP
ECE
ETPS
[1:0]
ETF[3:0]
MSM
TS[2:0]
Reserved
SMS[2:0]
Reset value 000000000000 000
0x0C
TIMx_DIER
Reserved
TDE
COMDE
CC4DE
CC3DE
CC2DE
CC1DE
UDE
Reserved
TIE
Reserved
CC4IE
CC3IE
CC2IE
CC1IE
UIE
Reset value 0000000 0 00000
0x10
TIMx_SR
Reserved
CC4OF
CC3OF
CC2OF
CC1OF
Reserved
TIF
Reserved
CC4IF
CC3IF
CC2IF
CC1IF
UIF
Reset value 0000 0 00000
0x14
TIMx_EGR
Reserved
TG
Reserved
CC4G
CC3G
CC2G
CC1G
UG
Reset value 0 00000
0x18
TIMx_CCMR1
Output Compare
mode
Reserved
OC2CE
OC2M
[2:0]
OC2PE
OC2FE
CC2S
[1:0]
OC1CE
OC1M
[2:0]
OC1PE
OC1FE
CC1S
[1:0]
Reset value 0000000000000000
TIMx_CCMR1
Input Capture
mode
Reserved
IC2F[3:0]
IC2
PSC
[1:0]
CC2S
[1:0]
IC1F[3:0]
IC1
PSC
[1:0]
CC1S
[1:0]
Reset value 0000000000000000
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