Embedded Flash memory interface RM0090
61/1422 Doc ID 018909 Rev 4
3.4 Read interface
3.4.1 Relation between CPU clock frequency and Flash memory read time
To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device.
The prefetch buffer must be disabled when the supply voltage is below 2.1 V. The
correspondence between wait states and CPU clock frequency is given in Table 7 .
Table 6. Flash memory organization (STM32F42x and STM32F43x)
Block Name Block base addresses Size
Main memory
Sector 0 0x0800 0000 - 0x0800 3FFF 16 Kbyte
Sector 1 0x0800 4000 - 0x0800 7FFF 16 Kbyte
Sector 2 0x0800 8000 - 0x0800 BFFF 16 Kbyte
Sector 3 0x0800 C000 - 0x0800 FFFF 16 Kbyte
Sector 4 0x0801 0000 - 0x0801 FFFF 64 Kbyte
Sector 5 0x0802 0000 - 0x0803 FFFF 128 Kbyte
Sector 6 0x0804 0000 - 0x0805 FFFF 128 Kbyte
- - -
- - -
- - -
Sector 11 0x080E 0000 - 0x080F FFFF 128 Kbyte
Sector 12 0x0810 0000 - 0x0810 3FFF 16 Kbyte
Sector 13 0x0810 4000 - 0x0810 7FFF 16 Kbyte
Sector 14 0x0810 8000 - 0x0810 BFFF 16 Kbyte
Sector 15 0x0810 C000 - 0x0810 FFFF 16 Kbyte
Sector 16 0x0811 0000 - 0x0811 FFFF 64 Kbyte
Sector 17 0x0812 0000 - 0x0813 FFFF 128 Kbyte
Sector 18 0x0814 0000 - 0x0815 FFFF 128 Kbyte
- -
- -
- -
Sector 23 0x081E 0000 - 0x081F FFFF 128 Kbyte
System memory 0x1FFF 0000 - 0x1FFF 77FF 30 Kbyte
OTP 0x1FFF 7800 - 0x1FFF 7A0F 528 bytes
Option bytes
0x1FFF C000 - 0x1FFF C00F 16 bytes
0x1FFE C000 - 0x1FFE C007 16 bytes
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