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ST STM32F40 Series User Manual

ST STM32F40 Series
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RM0090 USB on-the-go high-speed (OTG_HS)
Doc ID 018909 Rev 4 1170/1422
Host suspend
The application can decide to suspend the USB activity by setting the port suspend bit in the
host port control and status register (PSUSP bit in OTG_HS_HPRT). The OTG_HS core
stops sending SOFs and enters the Suspended state.
The Suspended state can be exited on the remote device initiative (remote wakeup). In this
case the remote wakeup interrupt (WKUPINT bit in OTG_HS_GINTSTS) is generated upon
detection of a remote wakeup event, the port resume bit in the host port control and status
register (PRES bit in OTG_HS_HPRT) is set, and a resume signaling is automatically issued
on the USB. The application must monitor the resume window duration, and then clear the
port resume bit to exit the Suspended state and restart the SOF.
If the Suspended state is exited on the host initiative, the application must set the port
resume bit to start resume signaling on the host port, monitor the resume window duration
and then clear the port resume bit.
31.6.3 Host channels
The OTG_HS core instantiates 12 host channels. Each host channel supports an USB host
transfer (USB pipe). The host is not able to support more than 8 transfer requests
simultaneously. If more than 8 transfer requests are pending from the application, the host
controller driver (HCD) must re-allocate channels when they become available, that is, after
receiving the transfer completed and channel halted interrupts.
Each host channel can be configured to support IN/OUT and any type of
periodic/nonperiodic transaction. Each host channel has dedicated control (HCCHARx),
transfer configuration (HCTSIZx) and status/interrupt (HCINTx) registers with associated
mask (HCINTMSKx) registers.
Host channel controls
The following host channel controls are available through the host channel-x characteristics
register (HCCHARx):
Channel enable/disable
Program the HS/FS/LS speed of target USB peripheral
Program the address of target USB peripheral
Program the endpoint number of target USB peripheral
Program the transfer IN/OUT direction
Program the USB transfer type (control, bulk, interrupt, isochronous)
Program the maximum packet size (MPS)
Program the periodic transfer to be executed during odd/even frames
Host channel transfer
The host channel transfer size registers (HCTSIZx) allow the application to program the
transfer size parameters, and read the transfer status.
The programming operation must be performed before setting the channel enable bit in the
host channel characteristics register. Once the endpoint is enabled, the packet count field is
read-only as the OTG HS core updates it according to the current transfer status.

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ST STM32F40 Series Specifications

General IconGeneral
BrandST
ModelSTM32F40 Series
CategoryMicrocontrollers
LanguageEnglish

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