ST STM32F40 Series User Manual

Reset and clock control for (RCC) RM0090
173/1422 Doc ID 018909 Rev 4
6.3.26 RCC APB2 peripheral clock enabled in low power mode register
for STM32F42xxx and STM32F43xxx (RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0007 5F33
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SPI6
LPEN
SPI5
LPEN
Reser-
ved
TIM11
LPEN
TIM10
LPEN
TIM9
LPEN
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reser-
ved
SYSC
FG
LPEN
SPI4
LPEN
SPI1
LPEN
SDIO
LPEN
ADC3
LPEN
ADC2
LPEN
ADC1
LPEN
Reserved
USART6
LPEN
USART1
LPEN
Reserved
TIM8
LPEN
TIM1
LPEN
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 SPI6LPEN: SPI6 clock enable during Sleep mode
Set and cleared by software.
0: SPI6 clock disabled during Sleep mode
1: SPI6 clock enabled during Sleep mode
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
Set and cleared by software.
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
Set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
Set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
Set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English