RM0090 DMA controller (DMA)
Doc ID 018909 Rev 4 236/1422
9.5.2 DMA high interrupt status register (DMA_HISR)
Address offset: 0x04
Reset value: 0x0000 0000
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No half transfer event on stream x
1: A half transfer event occurred on stream x
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No Direct Mode Error on stream x
1: A Direct Mode Error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No FIFO Error event on stream x
1: A FIFO Error event occurred on stream x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TCIF7 HTIF7 TEIF7 DMEIF7
Reserv
ed
FEIF7 TCIF6 HTIF6 TEIF6 DMEIF6
Reserv
ed
FEIF6
rr r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TCIF5 HTIF5 TEIF5 DMEIF5
Reserv
ed
FEIF5 TCIF4 HTIF4 TEIF4 DMEIF4
Reserv
ed
FEIF4
rr r r r r r r r r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No half transfer event on stream x
1: A half transfer event occurred on stream x
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