ST STM32F40 Series User Manual

Inter-integrated circuit (I
2
C) interface RM0090
739/1422 Doc ID 018909 Rev 4
25.6.9 I
2
C TRISE register (I2C_TRISE)
Address offset: 0x20
Reset value: 0x0002
Bits 11:0 CCR[11:0]: Clock control register in Fast/Standard mode (Master mode)
Controls the SCL clock in master mode.
Standard mode or SMBus
:
T
high
= CCR * T
PCLK1
T
low
= CCR * T
PCLK1
Fast mode:
If DUTY = 0:
T
high
= CCR * T
PCLK1
T
low
= 2 * CCR * T
PCLK1
If DUTY = 1: (to reach 400 kHz)
T
high
= 9 * CCR * T
PCLK1
T
low
= 16 * CCR * T
PCLK1
For instance: in standard mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, T
PCLK1
= 125 ns so CCR must be programmed with 0x28
(0x28 <=> 40d x 125 ns = 5000 ns.)
Note: 1. The minimum allowed value is 0x04, except in FAST DUTY mode where the
minimum allowed value is 0x01
. These timings are without filters.
. The CCR register must be configured only when the I
2
C is disabled (PE = 0).
151413121110987 654321 0
Reserved
TRISE[5:0]
rw rw rw rw rw rw
Bits 15:6 Reserved, must be kept at reset value
Bits 5:0 TRISE[5:0]: Maximum rise time in Fast/Standard mode (Master mode)
These bits must be programmed with the maximum SCL rise time given in the I
2
C bus
specification, incremented by 1.
For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and T
PCLK1
= 125 ns
therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order
to respect the t
HIGH
parameter.
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English