ST STM32F40 Series User Manual

RM0090 Reset and clock control for (RCC)
Doc ID 018909 Rev 4 114/1422
Figure 13. Clock tree
1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the device datasheet.
PLL
VCO
xN
/ P
/ Q
/ R
/ M
/1 to 5
PHY Ethernet
25 to 50 MHz
USB2.0 PHY
24 to 60 MHz
/2,20
MII_RMII_SEL in SYSCFG_PMC
AHB
PRESC
/ 1,2,..512
APBx
PRESC
/ 1,2,4,8,16
if (APBx presc = 1x1
else x2
LSE
ETH_MII_TX_CLK_MII
OTG_HS_SCL
PLLI2SCLK
FCLK Cortex
free-running clock
APBx
peripheral
clocks
APBx timer
clocks
48 MHz
clocks
USBHS
ULPI clock
Ethernet
PTP clock
MCO1
Peripheral
clock enable
/1 to 5
MCO2
ai16088c
ETH_MII_RX_
CLK_MII
OSC32_IN
OSC32_OUT
LSE OSC
32.768 kHz
LSI RC
32 kHz
to independent
watchdog
LSE
LSI
to RTC
RTCCLK
RTCSEL[1:0]
IWDGCLK
HSE OSC
4-26 MHz
OSC_IN
OSC_OUT
HSI RC
16 MHz
PLLCLK
HSI
HSI
HSE
SW
SYSCLK
168 MHz
max
HCLK
to AHB bus, core,
memory and DMA
168 MHz max.
to Cortex System
timer
/8
Clock
Enable
Peripheral
clock enable
PLL48CK
I2S clocks
Peripheral
clock enable
Peripheral
clock enable
MACRMIICLK
MACTXCLK
MACRXCLK
to Ethernet MAC
Peripheral
clock enable
Peripheral
clock enable
Watchdog
enable
RTC
enable
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
/2 to 31
PLLI2S
VCO
xN
/ P
/ Q
/ R
SYSCLK
Ext. clock
I2SSRC
HSE_RTC
HSE
I2S_CKIN

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English