ST STM32F40 Series User Manual

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
925/1422 Doc ID 018909 Rev 4
Figure 335. Transmission with collision
Figure 336 shows a frame transmission in MII and RMII.
Figure 336. Frame transmission in MMI and RMII modes
29.5.3 MAC frame reception
The MAC received frames are pushes into the Rx FIFO. The status (fill level) of this FIFO is
indicated to the DMA once it crosses the configured receive threshold (RTC in the
ETH_DMAOMR register) so that the DMA can initiate pre-configured burst transfers towards
the AHB interface.
In the default Cut-through mode, when 64 bytes (configured with the RTC bits in the
ETH_DMAOMR register) or a full packet of data are received into the FIFO, the data are
popped out and the DMA is notified of its availability. Once the DMA has initiated the transfer
to the AHB interface, the data transfer continues from the FIFO until a complete packet has
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
PR EAM BLE SFD
MII_CS
MII_COL
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DA DA JAM JAM JAM JAM
MII_RX_CLK
MII_TX_EN
MII_TXD[3:0]
RMII_REF_CLK
RMII_TXD[1:0]
RMII_TX_EN
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ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English