Flexible static memory controller (FSMC) RM0090
1357/1422 Doc ID 018909 Rev 4
32.6 NAND Flash/PC Card controller
The FSMC generates the appropriate signal timings to drive the following types of device:
● NAND Flash
–8-bit
– 16-bit
● 16-bit PC Card compatible devices
The NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support
NAND Flash devices. Bank 4 supports PC Card devices.
Each bank is configured by means of dedicated registers (Section 32.6.8). The
programmable memory parameters include access timings (shown in Ta bl e 2 1 5) and ECC
configuration.
Bits 15:8 DATAST: Data-phase duration.
These bits are written by software to define the duration of the data phase (refer to Figure 405 to
Figure 417), used in SRAMs, ROMs and asynchronous NOR Flash accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is don't care.
Bits 7:4 ADDHLD: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 414 to Figure 417), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash
accesses:
0000: Reserved
0001: ADDHLD phase duration = 1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0 ADDSET: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to Figure 414 to Figure 417), used in SRAMs, ROMs and asynchronous NOR Flash
accessed:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is don’t care.
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