ST STM32F40 Series User Manual

Reset and clock control for (RCC) RM0090
143/1422 Doc ID 018909 Rev 4
6.3.11 RCC APB2 peripheral reset register for
STM32F42xxx and STM32F43xxx (RCC_APB2RSTR)
Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
SPI6
RST
SPI5
RST
Res.
TIM11
RST
TIM10
RST
TIM9
RST
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reser-
ved
SYSCFG
RST
SPI4
RST
SPI1
RST
SDIO
RST
Reserved
ADC
RST
Reserved
USART6
RST
USART1
RST
Reserved
TIM8
RST
TIM1
RST
rw rw rw rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 SPI6RST: SPI6 reset
Set and cleared by software.
0: does not reset SPI6
1: resets SPI6
Bit 20 SPI5RST: SPI5 reset
Set and cleared by software.
0: does not reset SPI5
1: resets SPI5
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
Set and cleared by software.
0: does not reset TIM11
1: resets TIM14
Bit 17 TIM10RST: TIM10 reset
Set and cleared by software.
0: does not reset TIM10
1: resets TIM10
Bit 16 TIM9RST: TIM9 reset
Set and cleared by software.
0: does not reset TIM9
1: resets TIM9
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGRST: System configuration controller reset
Set and cleared by software.
0: does not reset the System configuration controller
1: resets the System configuration controller
Bit 13 SPI4RST: SPI4 reset
Set and cleared by software.
0: does not reset SPI4
1: resets SPI4

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English