RM0090 Analog-to-digital converter (ADC)
Doc ID 018909 Rev 4 304/1422
11.13.16 ADC common control register (ADC_CCR)
Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 OVR1: Overrun flag of ADC1
This bit is a copy of the OVR bit in the ADC1_SR register.
Bit 4 STRT1: Regular channel Start flag of ADC1
This bit is a copy of the STRT bit in the ADC1_SR register.
Bit 3 JSTRT1: Injected channel Start flag of ADC1
This bit is a copy of the JSTRT bit in the ADC1_SR register.
Bit 2 JEOC1: Injected channel end of conversion of ADC1
This bit is a copy of the JEOC bit in the ADC1_SR register.
Bit 1 EOC1: End of conversion of ADC1
This bit is a copy of the EOC bit in the ADC1_SR register.
Bit 0 AWD1: Analog watchdog flag of ADC1
This bit is a copy of the AWD bit in the ADC1_SR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
TSVREFE VBATE
Reserved
ADCPRE
rw rw rw rw
15141312111098 7 654321 0
DMA[1:0] DDS
Res.
DELAY[3:0]
Reserved
MULTI[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE: Temperature sensor and V
REFINT
enable
This bit is set and cleared by software to enable/disable the temperature sensor and the
V
REFINT
channel.
0: Temperature sensor and V
REFINT
channel disabled
1: Temperature sensor and V
REFINT
channel enabled
Note: On STM32F42x and STM32F43x devices, VBATE must be disabled when TSVREFE is
set. If both bits are set, only the VBAT conversion is performed.
Bit 22 VBATE: V
BAT
enable
This bit is set and cleared by software to enable/disable the V
BAT
channel.
0: V
BAT
channel disabled
1: V
BAT
channel enabled
Bits 21:18 Reserved, must be kept at reset value.
To Next Page
Loading...
Need help?
General
