ST STM32F40 Series

Reset and clock control for (RCC) RM0090
151/1422 Doc ID 018909 Rev 4
6.3.16 RCC APB1 peripheral clock enable register
for STM32F42xxx and STM32F43xxx(RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
Bit 2 TIM4EN: TIM4 clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART8
EN
UART7
EN
DAC
EN
PWR
EN
Reser-
ved
CAN2
EN
CAN1
EN
Reser-
ved
I2C3
EN
I2C2
EN
I2C1
EN
UART5
EN
UART4
EN
USART3
EN
USART2
EN
Reser-
ved
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Reserved
WWDG
EN
Reserved
TIM14
EN
TIM13
EN
TIM12
EN
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31 UART8EN: UART8 clock enable
Set and cleared by software.
0: UART8 clock disabled
1: UART8 clock enabled
Bits 30 UART7EN: UART7 clock enable
Set and cleared by software.
0: UART7 clock disabled
1: UART7 clock enabled
Bit 29 DACEN: DAC interface clock enable
Set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 Reserved, must be kept at reset value.