Real-time clock (RTC) RM0090
639/1422 Doc ID 018909 Rev 4
After a tamper event has been detected and cleared, the TAMPERx alternate function
should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the
backup registers (RTC_BKPxR). This prevents the application from writing to the backup
registers while the TAMPERx value still indicates a tamper detection. This is equivalent to a
level detection on the TAMPERx alternate function.
Note: Tamper detection is still active when V
DD
power is switched off. To avoid unwanted resetting
of the backup registers, the pin to which the TAMPER alternate function is mapped should
be externally tied to the correct level.
Level detection with filtering on tamper inputs
Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper
detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive
samples are observed at the level designated by the TAMPxTRG bits
(TAMP1TRG/TAMP2TRG).
The TAMPER inputs are pre-charged through the I/O internal pull-up resistance before its
state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge
is determined by the TAMPPRCH bits, allowing for larger capacitances on the tamper inputs.
The trade-off between tamper detection latency and power consumption through the pull-up
can be optimized by using TAMPFREQ to determine the frequency of the sampling for level
detection.
Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors.
TAMPER alternate function detection
The TAMPER1 alternate function (RTC_TAMP1) can be mapped either to RTC_AF1(PC13)
or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in RTC_TAFCR register (see
Section 23.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR)).
TAMPE bit must be cleared when TAMP1INSEL is modified to avoid unwanted setting of
TAMPF.
The TAMPER 2 alternate function corresponds to RTC_TAMP2 pin.
23.3.14 Calibration clock output
When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the
RTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and PREDIV_A
= 0x7F, the RTC_CALIB frequency is f
RTCCLK
/64. This corresponds to a calibration output at
512 Hz for an RTCCLK frequency at 32.768 kHz.
The RTC_CALIB output is not impacted by the calibration value programmed in
RTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling
edges. It is therefore recommended to use rising edges.
If COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] =
0xFF), the RTC_CALIB frequency is f
RTCCLK/(256 * (PREDIV_A+1)). This corresponds to a
calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S =
0xFF), with an RTCCLK frequency at 32.768 kHz.
Calibration alternate function output
When the COE bit in the RTC_CR register is set to 1, the calibration alternate function
(RTC_CALIB) is enabled on RTC_AF1.
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