Flexible static memory controller (FSMC) RM0090
1341/1422 Doc ID 018909 Rev 4
Figure 417. Multiplexed write accesses
The difference with mode D is the drive of the lower address byte(s) on the databus.
Table 209. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-21 Reserved 0x000
19 CBURSTRW 0x0 (no effect on asynchronous mode)
18:16 Reserved 0x0
15 ASYNCWAIT
Set to 1 if the memory supports this feature. Otherwise keep at
0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect on asynchronous mode)
12 WREN 0x1
11 WAITCFG As needed
10 WRAPMOD 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5-4 MWID As needed
3-2 MTYP 0x2 (NOR Flash memory)
A[25:16]
NOE
ADDSET (DATAST + 1)
Memory transaction
NEx
AD[15:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven by FSMC
ai15569
1HCLK
ADDHLD
HCLK cycles
Lower address
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