RM0090 Flexible static memory controller (FSMC)
Doc ID 018909 Rev 4 1340/1422
Muxed mode - multiplexed asynchronous access to NOR Flash memory
Figure 416. Multiplexed read accesses
Table 208. FSMC_BWTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x3
27-24 DATLAT 0x0
23-20 CLKDIV 0x0
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles) for
writer accesses
7-4 ADDHLD
Duration of the middle phase of the write access (ADDHLD HCLK
cycles)
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) for
write accesses. Minimum value for ADDSET is 0.
A[25:16]
NOE
ADDSET DATAST
Memory transaction
NEx
AD[15:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven
by memory
ai15568
High
ADDHLD
HCLK cycles
Lower address
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