RM0090 Debug support (DBG)
Doc ID 018909 Rev 4 1376/1422
The ARM Cortex™-M4F core provides integrated on-chip debug support. It is comprised of:
● SWJ-DP: Serial wire / JTAG debug port
● AHP-AP: AHB access port
● ITM: Instrumentation trace macrocell
● FPB: Flash patch breakpoint
● DWT: Data watchpoint trigger
● TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
● ETM: Embedded Trace Macrocell (available on larger packages, where the
corresponding pins are mapped)
It also includes debug features dedicated to the STM32F4xx:
● Flexible debug pinout assignment
● MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the ARM Cortex™-M4F core,
refer to the Cortex™-M4F-r0p1 Technical Reference Manual and to the CoreSight Design
Kit-r0p1 TRM (see Section 33.2: Reference ARM documentation).
33.2 Reference ARM documentation
● Cortex™-M4F r0p1 Technical Reference Manual (TRM)
(see Related documents on page 1)
● ARM Debug Interface V5
● ARM CoreSight Design Kit revision r0p1 Technical Reference Manual
33.3 SWJ debug port (serial wire and JTAG)
The STM32F4xx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM
standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-
pin) interface.
● The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port.
● The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
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