Flexible static memory controller (FSMC) RM0090
1339/1422 Doc ID 018909 Rev 4
The differences with mode1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Table 206. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 Reserved 0x000
19 CBURSTRW 0x0 (no effect on asynchronous mode)
18:16 Reserved 0x0
15 ASYNCWAIT
Set to 1 if the memory supports this feature. Otherwise keep
at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect on asynchronous mode)
12 WREN 0x1
11 WAITCFG As needed
10 WRAPMOD 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP As needed
1 MUXEN 0x0
0 MBKEN 0x1
Table 207. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x3
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles) in
read.
7-4 ADDHLD
Duration of the middle phase of the read access (ADDHLD HCLK
cycles)
3-0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) in read.
Minimum value for ADDSET is 0.
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