RM0090 Inter-integrated circuit (I
2
C) interface
Doc ID 018909 Rev 4 738/1422
Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was
set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found
set in I2C_SR1 or when the STOPF bit is cleared.
25.6.8 I
2
C Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note: f
PCLK1
must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least
4 MHz to achieve fast mode I²C frequencies. It must be a multiple of 10MHz to reach the
400 kHz maximum I²C fast mode clock.
The CCR register must be configured only when the I2C is disabled (PE = 0).
Bit 0 MSL: Master/slave
0: Slave Mode
1: Master Mode
–Set by hardware as soon as the interface is in Master mode (SB=1).
–Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
(ARLO=1), or by hardware when PE=0.
151413121110987 654321 0
F/S DUTY
Reserved
CCR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 F/S: I2C master mode selection
0: Standard Mode I2C
1: Fast Mode I2C
Bit 14 DUTY: Fast mode duty cycle
0: Fast Mode t
low
/t
high
= 2
1: Fast Mode t
low
/t
high
= 16/9 (see CCR)
Bits 13:12 Reserved, must be kept at reset value
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