RM0090 DMA controller (DMA)
Doc ID 018909 Rev 4 238/1422
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
CTCIF7 CHTIF7 CTEIF7 CDMEIF7
Reserved
CFEIF7 CTCIF6 CHTIF6 CTEIF6 CDMEIF6
Reserved
CFEIF6
www w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CTCIF5 CHTIF5 CTEIF5 CDMEIF5
Reserved
CFEIF5 CTCIF4 CHTIF4 CTEIF4 CDMEIF4
Reserved
CFEIF4
www w w w w w w w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register
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