Hash processor (HASH) RM0090
611/1422 Doc ID 018909 Rev 4
Bits 5:4 DATATYPE: Data type selection
Defines the format of the data entered into the HASH_DIN register:
00: 32-bit data. The data written into HASH_DIN are directly used by the HASH
processing, without reordering.
01: 16-bit data, or half-word. The data written into HASH_DIN are considered as
2 half-words, and are swapped before being used by the HASH processing.
10: 8-bit data, or bytes. The data written into HASH_DIN are considered as 4
bytes, and are swapped before being used by the HASH processing.
11: bit data, or bit-string. The data written into HASH_DIN are considered as 32
bits (1st bit of the sting at position 0), and are swapped before being used by the
HASH processing (1st bit of the string at position 31).
Bit 3 DMAE: DMA enable
0: DMA transfers disabled
1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is
ready to receive data.
Note: 1: This bit is cleared by hardware when the DMA asserts the DMA terminal
count signal (while transferring the last data of the message). This bit is not
cleared when the INIT bit is written to 1.
2: If this bit is written to 0 while a DMA transfer has already been requested
to the DMA, DMAE is cleared but the current transfer is not aborted.
Instead, the DMA interface remains internally enabled until the transfer is
complete or INIT is written to 1.
Bit 2 INIT: Initialize message digest calculation
Writing this bit to 1 resets the hash processor core, so that the HASH is ready to
compute the message digest of a new message.
Writing this bit to 0 has no effect.
Reading this bit always return 0.
Bit 1:0 Reserved, must be kept cleared.
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