Freescale Semiconductor MPC5604B - Slow Internal RC Oscillator (SIRC) Digital Interface

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 99
NOTE
The 32 KHz slow external crystal oscillator is by default always ON, but
can be configured OFF in standby by setting the OSCON bit.
6.5 Slow internal RC oscillator (SIRC) digital interface
6.5.1 Introduction
The SIRC digital interface controls the 128 kHz slow internal RC oscillator (SIRC). It holds control and
status registers accessible for application.
6.5.2 Functional description
The SIRC provides a low frequency (f
SIRC
) clock of 128 kHz requiring very low current consumption.
This clock can be used as the reference clock when a fixed base time is required for specific modules.
SIRC is always on in all device modes except STANDBY mode. In STANDBY mode, it is controlled by
SIRC_CTL[SIRCON_STDBY] bit. The clock source status is updated in SIRC_CTL[S_SIRC] bit.
The SIRC clock can be further divided by a configurable division factor in the range from 1 to 32 to
generate the divided clock to match system requirements. This division factor is specified by
SIRC_CTL[SIRCDIV] bits.
The SIRC output frequency can be trimmed using SIRC_CTL[SIRCTRIM]. After a power-on reset, the
SIRC is trimmed using a factory test value stored in test flash memory. However, after a power-on reset
Table 6-5. SXOSC_CTL field descriptions
Field Description
OSCBYP Crystal Oscillator bypass.
This bit specifies whether the oscillator should be bypassed or not.
0 Oscillator output is used as root clock.
1 OSC32K_EXTAL is used as root clock.
EOCV End of Count Value.
This field specifies the end of count value to be used for comparison by the oscillator stabilization
counter OSCCNT after reset or whenever it is switched on from the off state. This counting period
ensures that external oscillator clock signal is stable before it can be selected by the system. When
oscillator counter reaches the value EOCV × 512, the crystal oscillator status (S_OSC) is set. The
OSCCNT counter will be kept under reset if oscillator bypass mode is selected.
OSCDIV Crystal oscillator clock division factor.
This field specifies the crystal oscillator output clock division factor. The output clock is divided by
the factor OSCDIV + 1.
S_OSC Crystal oscillator status.
0 Crystal oscillator output clock is not stable.
1 Crystal oscillator is providing a stable clock.
OSCON Crystal oscillator enable.
0 Crystal oscillator is switched off.
1 Crystal oscillator is switched on.