Freescale Semiconductor MPC5604B - B.3 Changes between Revisions 4 and 5

MPC5604B/C Microcontroller Reference Manual, Rev. 8
910 Freescale Semiconductor
B.3 Changes between revisions 4 and 5
Table B-3. Changes between revisions 4 and 5
Chapter Description
Throughout Editorial changes and improvements.
Overview “MPC5604B series block diagram”figure:
– Added “Interrupt request with wake-up functionality” as an input to the WKPU block.
Signal Description “Functional port pin description” table:
– Improved the footnote regarding JTAGC pins in order to explain when the device get
incompliance with IEEE 1149.1-2001.
– Added a footnote concerning the family compatibility.
– Footnote 11: Replaced MPC5603B with MPC5602B
Clock Description “MPC5604B System Clock Generation” figure:
– Changed the dividers from 1 to 15 to 1 to 16 of the system clock selectors.
“Progressive clock switching” section:
– Revised.
– Added “Progressive clock switching scheme” figure.
– Update definition of en_pll_sw bit filed on Control Register.
“Slow external crystal oscillator (SXOSC) digital interface“ section:
– Interrupt functionalities are not available on SXOSC.
Boot Assist Module “Hardware configuration to select boot mode“ table:
– Renamed the flag "Standby-RAM Boot Flag" to "BOOT_FROM_BKP_RAM".
“Download 64-bit password and password check“ section:
– Added note about password management.
“Boot from FlexCAN“ section:
– Added note about the distirb provided by CAN traffic.
Interrupt Controller Replaced INTC_PSR121 with “INTC_PSR147
Updated “INTC Priority Select Registers“ and “INTC Priority Select Register Address
Offsets“ table in according to “Interrupt Vector Table“ table
IEEE 1149.1 Test
Access Port Controller
“External Signal Description“ section:
– Emphasized when the device get incompliance with IEEE 1149.1-2001.
Nexus Development
Interface
“Ownership Trace“ section:
– Added it.
Flash Memory – Updated delivery values of NVPWD0 and NVPWD1 for Code Flash.
– Revised the “Margin read“ section for both Flash.
– Replaced “Margin Mode“ with “Margin Read”.
Deserial Serial
Peripheral Interface
“DSPIx_MCR register“:
– Included Bit fields CLR_TXF and CLR_RXF.
LIN Controller “LINTCSR“ register:
– Updated the reset value.
FlexCAN “Control Register (CTRL) field description” table:
– Sorted correctly the bit fields.