MPC5604B/C Microcontroller Reference Manual, Rev. 8
428 Freescale Semiconductor
Table 22-3 shows a Standard/Extended Message Buffer (MB0) memory map, using 16 bytes total
(0x80–0x8F space).
22.3.2 Message buffer structure
The Message Buffer structure used by the FlexCAN module is represented in Table 22-2. Both Extended
and Standard Frames (29-bit Identifier and 11-bit Identifier, respectively) used in the CAN specification
(Version 2.0 Part B) are represented.
Table 22-3. Message buffer MB0 memory mapping
Address offset MB field
0x80 Control and Status (C/S)
0x84 Identifier Field
0x88–0x8F Data Field 0 – Data Field 7 (1 byte each)
012345678910111213141516171819202122232425262728293031
0x0 CODE
SRR
IDE
RTR
LENGTH TIME STAMP
0x4 PRIO ID (Standard/Extended) ID (Extended)
0x8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3
0x
C
Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
= Unimplemented or Reserved
Figure 22-2. Message Buffer Structure
Table 22-4. Message Buffer Structure field description
Field Description
CODE Message Buffer Code
This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as
part of the message buffer matching and arbitration process. The encoding is shown in Table 2 2-5
and Table 22-6. See Section 22.4, “Functional description for additional information.
SRR Substitute Remote Request
Fixed recessive bit, used only in extended format. It must be set to ‘1’ by the user for transmission
(Tx Buffers) and will be stored with the value received on the CAN bus for Rx receiving buffers. It
can be received as either recessive or dominant. If FlexCAN receives this bit as dominant, then it is
interpreted as arbitration loss.
1 = Recessive value is compulsory for transmission in Extended Format frames
0 = Dominant is not a valid value for transmission in Extended Format frames
IDE ID Extended Bit
This bit identifies whether the frame format is standard or extended.
1 = Frame format is extended
0 = Frame format is standard
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