Freescale Semiconductor MPC5604B - Chapter 13 Device-Specific Information

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 245
Figure 13-2. Clock gating for RTC clocks
13.3 Device-specific information
For MPC5604B, the device specific information is the following:
• SXOSC, FIRC and SIRC clocks are provided as counter clocks for the RTC. Default clock on reset
is SIRC divided by 4.
• The RTC will be reset on destructive reset, with the exception of software watchdog reset.
• The RTC provides a configurable divider by 512 to be optionally used when FIRC source is
selected.
13.4 Modes of operation
13.4.1 Functional mode
There are two functional modes of operation for the RTC: normal operation and low power mode. In
normal operation, all RTC registers can read or written and the input isolation is disabled. The RTC/API
32-bit counter
CELL
C.G.
en
SIRC
(cnten & clksel== 2’b00)
CELL
en
SXOSC
(cnten & clksel== 2’b01)
CELL
en
FIRC
(cnten & clksel== 2’b10)
CELL
C.G.
en
Reserved
(cnten & clksel== 2’b11)
C.G.
C.G.
0 1
2
CLKSEL[0:1]
3
CELL
C.G.
en
1
0
div 512
CELL
C.G.
en
1
0
div 32
div512en
div32en
CNTEN