Freescale Semiconductor MPC5604B - Flexcan Addressing and SRAM Size Configurations

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 467
For any configuration change/initialization it is required that FlexCAN is put into Freeze Mode (see
Section 22.4.10.1, “Freeze Mode). The following is a generic initialization sequence applicable to the
FlexCAN module:
• Initialize the Module Configuration Register
— Enable the individual filtering per MB and reception queue features by setting the BCC bit
— Enable the warning interrupts by setting the WRN_EN bit
— If required, disable frame self reception by setting the SRX_DIS bit
— Enable the FIFO by setting the FEN bit
— Enable the abort mechanism by setting the AEN bit
— Enable the local priority feature by setting the LPRIO_EN bit
• Initialize the Control Register
— Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
— Determine the bit rate by programming the PRESDIV field
— Determine the internal arbitration mode (LBUF bit)
• Initialize the Message Buffers
— The Control and Status word of all Message Buffers must be initialized
— If FIFO was enabled, the 8-entry ID table must be initialized
— Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the IMASK Registers (for all MB interrupts) and in CTRL
Register (for Bus Off and Error interrupts)
• Negate the HALT bit in MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
22.5.2 FlexCAN addressing and SRAM size configurations
There are three SRAM configurations that can be implemented within the FlexCAN module. The possible
configurations are:
• For 16 MBs: 288 bytes for MB memory and 64 bytes for Individual Mask Registers
• For 32 MBs: 544 bytes for MB memory and 128 bytes for Individual Mask Registers
• For 64 MBs: 1056 bytes for MB memory and 256 bytes for Individual Mask Registers
In each configuration the user can program the maximum number of MBs that will take part in the
matching and arbitration processes using the MAXMB field in the MCR. For 16 MB configuration,
MAXMB can be any number between 0–15. For 32 MB configuration, MAXMB can be any number
between 0–31. For 64 MB configuration, MAXMB can be any number between 0–63.